Data Sheet S13368EJ3V0DS00

16

µµµµ PD16682

6. DISPLAY DATA RAM

6.1 Display Data RAM

This is the RAM that is used to store the display’s dot data. The RAM configuration is 65 (8 pages x 8 bits + 1) x

132 bits. Any specified bit can be accessed by selecting the corresponding page address and column address.

As is shown in Figure 6

the LCD, so that if a multiple set of

µPD16682 chips is used, there are fewer constraints on transfers of display data

and relatively more freedom for display configurations.

The MPU accesses the display data RAM for read/write operations via the I/O buffer, and these operations are

independent of the LCD driver signal read operations. Therefore, there are absolutely no adverse effects (such as

flicker) in the display when display data RAM is accessed asynchronously in relation to the LCD contents.

Figure 6

LCD data

LCD display

0

111

0

1

000

0

0

000

0

0

111

0

1

000

0

...

...

6.2 Page Address Circuit

The page address set command specifies the page address in the display data RAM, as is shown in Figure 6

access a different page, simply specify a different page address using this command.

is valid.

6.3 Column Address Circuit

The column address set command specifies the column address in the display data RAM, as is shown in Figure

6

MPU is able to successively access display data.

Incrementation of the column address stops at 83H. The column address and page address are mutually

independent, which means that to switch from column 83H on page 0 to column 00H on page 1, both the page

address and column address must be separately specified again.

Also, as is shown in Table 6

the correspondence between the display data RAM’s column address and segment output. This reduces the number

of IC layout constraints that are imposed when setting up the LCD module.

Table 6

SEG Output

ADC

“0”

00H

→

Column Address

→

83H

“1”

83H

←

Column Address

←

00H