AN4218 datasheet(14/26 Pages) STMICROELECTRONICS

14 / 26 page

Good practices of system power supply

AN4218

14/26

DocID024014 Rev 2

During the VBAT drop to 3.2 V, V1 (VDD) goes to 0 V and switches on after VBAT has reached

L99PM62GXP reset threshold. In this case the NRESET output is pulled low and goes to

high 2 ms after V1 has reached the NRESET high threshold.

Conclusion

The steep drop of V1 to 0 V in addition with the fast rising slope of V1 after VBAT has

recovered ensures a correct power-up reset of the microcontroller.

The NRESET output goes low to put the microcontroller into reset condition; it goes to high

after V1 has reached the microcontrollers operating region.

The correct power-down / power-up sequence ensures that the microcontroller is always in

a defined state. This is additionally supported by the NRESET signal.

Supply voltage slow ramp-up

Figure 13. VS voltage ramp up (0.5 V/min)

Line 1 (RESET): NRESET output

Line 2 (V1): microcontroller power supply VDD

Line 4 (VBAT): system power supply (VBAT)

As long as VBAT is below the L99PM62GXP reset threshold, V1 remains at 0 V. After VBAT

has reached the reset threshold of 3.1 V, V1 is switched on with a fast slope. As soon as the

NRESET threshold is reached NRESET goes to high.

Conclusion

The fast slope of V1 above the power-up-reset threshold of the microcontroller ensures a

correct power-up-reset of the microcontroller, depending only on the capacitors at the V1

node and not on the battery voltage slope.

AN4218 Datasheet(PDF) 14 Page - STMicroelectronics