AN2021 datasheet(28/39 Pages) STMICROELECTRONICS

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New registers

AN2021

28/39

New registers

4.1

XADRS3 register

On previous ST10 devices, this register was already present but its value was mask

programmed. On the ST10F272 this register has been made available to the user. In this

way the address range of the XRAM2 memory is now user-programmable.

The register functionality is the same as that of ADDRSELx registers used for external

address range selection, with some limitations:

●

The address window can only be located in the first megabyte of addressable space,

that is, in the 00’0000h-0F’FFFFh range

●

The window start address must be aligned to a Range Size boundary

4.1.1

Hardware impact

None.

ST10F272: XADRS3 (F01Ch)

SFR

Reset value: 800Bh

98765

4321

RGSAD

RGSZ

R/W

Table 16.

XADRS3 register description

Bit

Bit name

Function

15:4

RGSAD

Range Start Address

Defines the bits A19..A8 of the start address of the address window.

3:0

RGSZ

Range Size Selection

Defines the size of the address window.

Table 17.

Definition of address area

Bit field

RGSZ

Selected window

size

Relevant bit (R) of

RGSAD

Selected range Start Address

Relevant bit (R) of Address (A23 - A0)

0 0 0 0

256 bytes

RRRR RRRR RRRR

0000 RRRR RRRR RRRR xxxx xxxx

0 0 0 1

512 bytes

RRRR RRRR RRRx

0000 RRRR RRRR RRRx xxxx xxxx

...

1 0 1 0

256 Kbytes

RRxx xxxx xxxx

0000 RRxx xxxx xxxx xxxx xxxx

1 0 1 1

512 Kbytes

Rxxx xxxx xxxx

0000 Rxxx xxxx xxxx xxxx xxxx

1 1 x x

Reserved

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