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UPD17207GF Datasheet(PDF) 45 Page - NEC |
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UPD17207GF Datasheet(HTML) 45 Page - NEC |
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45 / 120 page ![]() µPD17201A, 17207 45 8.3 WATCHDOG TIMER OPERATION TIMING Unless the watchdog timer is reset in a fixed time, the WDOUT pin outputs a low level. By connecting the WDOUT pin to the RESET pin, a program hang-up can be detected by the watchdog timer. To reset the watchdog timer, set WDTRES (WDTRES = 1). To disable hang-up detection by the watchdog timer when the subclock is used, program so that WDTRES is set at intervals of approximately 340 ms or less. Cautions 1. The watchdog timer cannot be reset in the shaded range in Fig. 8-3. Therefore, set the watchdog timer before both the fW/2 13 and fW/214 signals go high. 2. For further information on the WDOUT pin, also refer to 14. RESET. Fig. 8-3 Watchdog Timer Operation Timing Remark Figures in the parentheses indicate the value when using the subclock. fw/2 11 (16Hz) fw/2 12 (8Hz) fw/2 13 (4Hz) fw/2 14 (2Hz) INTWTM (at 4Hz) INTWTM (at 16Hz) WDOUT Watchdog timer reset signal WDTRES Setting WDTRES is invalid during this period WDOUT output goes low if WDTRES is not set |
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