SD3.0 constrains

AN4541

14/21

DocID026513 Rev 1

The clock signal waveform is shown in Figure 21.

Figure 21. Clock signal on the SD3.0 tested link with EMIF06-MSD04F3 and its demo

PCB

The characteristics of the Host are adapted to ensure the system obtains the best balance,

even if the added filter does not impact the link greatly: the data rate only decreases from

62.3-61.1 MB/s to 61.4-60.5 MB/s.

We can therefore conclude that the filter alone between the host and the card can maintain

the maximum capacitance value of the link below the maximum recommended value, which

in turn guarantees the maximum data rate of the card.

The EMIF06-MSD04F3, loaded with 10 pF (capacitance equivalent to the SD card) and

Figure 22. Its shows that rise and fall times are in accordance with the SD3.0 standard.