UPD17218CT datasheet(39/84 Pages) NEC

39 / 84 page

µPD17215, 17216, 17217, 17218

INTERRUPT FUNCTIONS

7.1

Interrupt Sources

µPD17217 is provided with three interrupt sources.

When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which

is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1.

Table 7-1 Vector Address

Priority

Interrupt Source

Ext/Int

Vector Address

8-bit timer

Internal

0003H

INT pin rising and falling edges

External

0002H

Basic interval timer

Internal

0001H

When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from

the one with the highest priority.

Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an

interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an

interrupt is accepted, the interrupt is disabled.

To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the

RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has

been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions.

Caution:

In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack

by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when

peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved

by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF

and WR be saved by software to RAM, and immediately before finishing interrupt processing the

saved contents be returned to thier original location.

UPD17218CT Datasheet(PDF) 39 Page - NEC