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UPD17231MC Datasheet(PDF) 2 Page - NEC |
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UPD17231MC Datasheet(HTML) 2 Page - NEC |
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2 / 92 page  Data Sheet U14360EJ1V0DS00 µPD17230, 17231, 17232, 17233, 17234, 17235, 17236 2 APPLICATION Preset remote controllers, toys, portable systems, etc. ORDERING INFORMATION Part Number Package µPD17230MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17231MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17232MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17233MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17234MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17235GT-××× 28-pin plastic SOP (375 mil) µPD17235MC-×××-5A4 30-pin plastic shrink SOP (300 mil) µPD17236GT-××× 28-pin plastic SOP (375 mil) µPD17236MC-×××-5A4 30-pin plastic shrink SOP (300 mil) Remark ××× indicates ROM code suffix. DIFFERENCE BETWEEN µPD17236 SUBSERIES AND µPD17225 SUBSERIES Item µPD17236 Subseries µPD17225 Subseries ROM capacity µPD17230: 2048 × 16 bits µPD17225: 2048 × 16 bits µPD17231: 4096 × 16 bits µPD17226: 4096 × 16 bits µPD17232: 6144 × 16 bits µPD17227: 6144 × 16 bits µPD17233: 8192 × 16 bits µPD17228: 8192 × 16 bits µPD17234: 10240 × 16 bits µPD17235: 12288 × 16 bits µPD17236: 16384 × 16 bits Port P0B0-P0B3: I/O (bit I/O) P0B0-P0B3: Input P0C0-P0C3: I/O (group I/O) P0C0-P0C3: Output P0D0-P0D3: I/O (group I/O) P0D0-P0D3: Output P1A0: Input or output selectable by mask option Reset RESET pin is internally pulled down by Low level is output from WDOUT pin by • Reset by watchdog timer occurrence of the internal reset signals on the occurrence of the internal reset signals on the • Reset by stack pointer left, and reset takes place (usually, RESET pin left, and reset takes place if the WDOUT pin • Low-voltage detection is pulled up). is externally connected to the RESET pin. circuit (mask option) STOP mode release <1> When any of pins P0A0-P0A3 goes low When any of P0A0-P0A3 or P0B0-P0B3 goes condition <2> When P0B0-P0B3, P0C0-P0C3, and low P0D0-P0D3 are used as input pins and any of them goes low <3> When the interrupt request (IRQ) of an interrupt for which IP flag is set is generated at rising or falling edge of INT pin Carrier frequency Selected by mask option 7.8 kHz to 1 MHz (fX = 4 MHz) <1> If carrier generation clock (RfX) is fX/2: 7.8 kHz to 1 MHz <2> If carrier generation clock (RfX) is fX: 15.6 kHz to 2 MHz Pin 14 P1A0 pin WDOUT pin |
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