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UPD178016A Datasheet(PDF) 21 Page - NEC |
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UPD178016A Datasheet(HTML) 21 Page - NEC |
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21 / 56 page  21 µPD178004A, 178006A, 178016A, 178018A 5.7 PLL FREQUENCY SYNTHESIZER Figure 5-10. PLL Frequency Synthesizer Block Diagram Internal Bus Internal Bus PLL Mode Select Register PWM Data Transfer Register PLL NS0 PLL MD0 PLL MD1 PLL RF2 PLL RF1 PLL RF0 PLL UL0 EO Select Register PLL Reference Mode Register PLL Unlock FF Judge Register PLL RF3 2 Input Select Block Programmable Divider Phase Comparator ( -DET) Unlock FF Reference Frequency Generator 4.5 MHz 4 Charge Pump EO1 EO0 VCOH VCOL Mixer 2 fN fr PLL Data Register (PLLRL, PLLRH, PLLR0) φ Voltage Control Generator Low pass Filter Note Note EOC ON1 EOC ON0 Note External circuit Cautions 1. Be sure to set EOCON0 to 0. 2. For the µPD178004A and 178006A, do not set EOCON1 to 1. |
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