UPD178018 datasheet(10/56 Pages) NEC

10 / 56 page

µPD178004, 178006, 178016, 178018

3.2 PINS OTHER THAN PORT PINS

Pin Name

I/O

Function

After Reset Alternate Function

INTP0-INTP6 Input

External maskable interrupt inputs with specifiable valid edges (rising

Input

P00-P06

edge, falling edge, both rising and falling edges).

SI0

Input

Serial interface serial data input

Input

P25/SB0/SDA0

SI1

P20

SO0

Output

Serial interface serial data output

Input

P26/SB1/SDA1

SO1

P21

SB0

I/O

Serial interface serial data input/output

Input

P25/SI0/SDA0

SB1

P26/SO0/SDA1

SDA0

P25/SI0/SB0

SDA1

P26/SO0/SB1

SCK0

I/O

Serial interface serial clock input/output

Input

P27/SCL

SCK1

P22

SCL

P27/SCK0

STB

Output

Serial interface automatic transmit/receive strobe output

Input

P23

BUSY

Input

Serial interface automatic transmit/receive busy input

Input

P24

TI1

Input

External count clock input to 8-bit timer (TM1)

Input

P33

TI2

External count clock input to 8-bit timer (TM2)

P34

BEEP

Output

Buzzer output

Input

P36

ANI0-ANI5

Input

A/D converter analog input

Input

P10-P15

PWM0-PWM2 Output

PWM output

—

P132-P134

EO0, EO1

Output

Error out output from charge pump of the PLL frequency synthesizer

—

VCOL

Input

Inputs PLL local band frequency (In HF, MF mode)

—

VCOH

Input

Inputs PLL local band frequency (In VHF mode)

—

AMIFC

Input

Inputs AM intermediate frequency counter

—

FMIFC

Input

Inputs FM intermediate frequency counter

—

RESET

Input

System reset input

—

Input

System clock oscillation resonator connection

—

——

REGOSC

—

Oscillation regulator. Connected to GND via a 0.1-

µF capacitor.

—

REGCPU

—

CPU power supply regulator. Connected to GND via a 0.1-

µF capacitor.

—

VDD

—

Positive power supply

—

GND

—

Ground

——

VDDPORT

—

Positive power supply for port block

—

GNDPORT

—

Ground for port block

—

VDDPLL

—

Positive power supply for PLL

—

GNDPLL

—

Ground for PLL

—

Internally connected. Connected to GND or GNDPORT.

—

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