UPD178016GC datasheet(16/56 Pages) NEC

16 / 56 page

µPD178004, 178006, 178016, 178018

5.2 CLOCK GENERATOR

The instruction execution time can be changed as follows.

0.44

µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (@ 4.5-MHz crystal oscillator with system clock.)

Figure 5-1. Clock Generator Block Diagram

fXX

Prescaler

System

Clock

Oscillator

Clock to peripheral

hardware other than

the above.

Clock to the PLL

frequency synthesizer,

basic timer and buzzer

output control circuit.

CPU Clock

(fCPU)

Standby

Control

Circuit

Wait Control

Circuit

To INTP0

Sampling Clock

fXX

Prescaler

Selector

STOP

Scaler

5.3 TIMER

The

µPD178004, 178006, 178016 and 178018 incorporate 5 channels of the timer.

• Basic timer

: 1 channel

• 8-bit timer/event counter

: 2 channel

• 8-bit timer (D/A converter) Note

: 1 channel

• Watchdog timer

: 1 channel

Note

Used is shared with the 8/9-bit resolution

× 3-channel D/A converter (PWM output).

FIGURE 5-2. Basic Timer Block Diagram

Divider

4.5 MHz

INTTMC

UPD178016GC Datasheet(PDF) 16 Page - NEC

UPD178016GC Datasheet(HTML) 16 Page - NEC

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