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LT1948 Datasheet(PDF) 3 Page - Linear Technology

Part # LT1948
Description  DC/DC Converter for TFT-LCD Panels
PDF  4 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1948 Datasheet(HTML) 3 Page - Linear Technology

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LT1948
3
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect
resistor divider tap here. Set AVDD according to AVDD =
1.26V(1 + R1/R2).
CT (Pin 2): Timing Capacitor Pin. Connect a 22nF capacitor
from CT to ground to program a 3ms delay from FB1
reaching 1.26V to VON turning on.
SW1 (Pin 3): AVDD Switch Node. Connect inductor and D1
here (see Figure 1). Minimize trace area at this pin to keep
EMI down.
GND (Pin 4): Ground. Connect directly to local ground
plane.
VIN (Pin 5): Input Supply Pin. Must be bypassed with a
ceramic capacitor close to the pin.
SW2 (Pin 6): VO2 Switch Node. Connect inductor and D2
here. Minimize trace area at this pin to keep EMI down.
VO2 (Pin 7): Sense Pin for 23V Output. Connect to VO2
output capacitor. This node is also internally connected to
the emitter of Q3 (see Block Diagram), the high side switch
between VO2 and VON.
VON (Pin 8): This is the Delayed 23V Output. VON becomes
23V after the internal timer times out.
To best understand operation of the LT1948, please refer
to the LT1948 Block Diagram. The device contains two
switching regulators, a timer and a high side switch. Three
outputs can be generated: an adjustable AVDD output, a
charge-pumped inversion of the AVDD output, called VOFF,
and a 23V/15mA output, called VON. Q3 keeps VON off for
an externally set time interval, set by a capacitor connected
to the CT pin.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AVDD switcher is current
limited at 1.5A, while the second VON switcher is limited to
800mA. They share the same 1.26V reference voltage.
1948 F02
1
2
8
7
3
4
6
5
L3
R1
R2
C1
D1
VON
VIN
VOFF
D4B
D3A
L1–L2
C4
C3
D2
C2
C6
GND
AVDD
OPERATIO
Figure 2. Recommended Component Placement
When the input voltage is below approximately 2.4V, an
undervoltage lockout circuit disables switching.
When AVDD is less than its final voltage, Q4 is turned on,
holding the CT pin at ground. When AVDD reaches final
value, Q4 lets go of the CT pin, allowing the 5.5µA current
source to charge the external capacitor, CT. When the
voltage on the CT pin reaches 1.25V, Q3 turns on, connect-
ing VO2 to VON. Capacitor value can be calculated using
the following formula:
C = (5.5
µA • tDELAY)/1.25V
A 22nF capacitor results in approximately 3ms of delay.



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