3850 datasheet(21/103 Pages) RENESAS

21 / 103 page

Rev.3.01

2003.06.20

page 19 of 98

3850 Group (Spec.H)

Fig. 13 Port block diagram (1) (spec. H)

Port latch

(1) Port P00

(2) Port P01

P01/SOUT2 P-channel output disable bit

P02/SCLK2 P-channel output disable bit

Direction

Port latch

Direction

Port latch

Direction

Port latch

Direction

Port latch

Direction

Port latch

Direction

Port latch

Direction

Port latch

Data bus

Serial I/O2 input

Serial I/O2 output

Serial I/O2 Transmit completion signal

Serial I/O2 port selection bit

(3) Port P02

Serial I/O2 synchronous

clock selection bit

Serial I/O2 port selection bit

Serial I/O2 clock output

Serial I/O2 external clock input

(4) Port P03

Serial I/O2 ready output

SRDY2 output enable bit

(5) Ports P04-P07,P1

(6) Port P20

Port XC switch bit

Oscillator

Port XC switch bit

Port P21

(7) Port P21

Port XC switch bit

Data bus

Sub-clock generating circuit input

(8) Ports P22,P23

Data bus

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