AN2014 datasheet(10/65 Pages) STMICROELECTRONICS

10 / 65 page

EEPROM cell and memory array architecture

AN2014

10/65

DocID10701 Rev 10

In fact, higher voltages, in the range 15 to 18V, are normally used, to reduce the time taken

for the operation. Voltages higher than this cannot be used, since they would damage the

thin Tunnel Oxide.

For erase, the cell Control Gate is made positive, and the source-drain region is grounded

(as shown in Figure 6). The electric field makes electrons move from the substrate towards

the floating gate, thereby filling the reservoir, and increasing the characteristic threshold

voltage of the transistor (as shown in Figure 3).

Figure 6. During erase, electrons go through the tunnel oxide into the floating gate

1. Characteristic threshold Vth increases and becomes positive as shown in Figure 3

For write, the Control Gate is grounded and the source-drain region is made positive (as

shown in Figure 7). The electric field is the opposite of that for erase, and so electrons move

out from the floating gate, thereby emptying the reservoir, and decreasing the characteristic

threshold voltage of the transistor (as shown in Figure 4).

Figure 7. During write, electrons go through the tunnel oxide out of the floating gate

1. Characteristic threshold decreases and becomes negative as shown in Figure 4.

Typically EEPROM erase/write cycles require a high voltage of about 15 to 18V for

approximately 5ms.

AI10232

Vg=+18V

Vd=0V

Electric Field

Tunneling Electrons

Control Gate

Source

Drain

Gate Oxide

Oxide

Channel Region

Floating Gate

AI10233

Vg=0V

Vd=+18V

Electric Field

Tunneling Electrons

Control Gate

Source

Drain

Gate Oxide

Oxide

Channel Region

Floating Gate

AN2014 Datasheet(PDF) 10 Page - STMicroelectronics

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