AN2442

DMA unit

5/22

1.2

Peripheral DMA support

Peripherals supporting the DMA are shown in this block diagram:

Figure 1.

DMAC and peripherals with DMA support

Note:

1

An external DMA request can be generated from 2 GPIO pins going to high levels.

The DMAC requests and triggering events are summarized in the following table:

Table 1.

STR91x DMA requests

ARM Core

USB

VIC

EMI

APB

External

TIM0

SSP0

UART0

Bridge

SSP1

UART1

TIM1

Memory

Channel7

2xExternal DMA Requests 1)

AHB Bus

APB Bus

RAM

IRQ

FIQ

FIFO

Channel6

Channel5

Channel2

Channel3

Channel1

Channel4

Channel0

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

DMA Interrupt Request

DMA Controller

DMA Request0:Pin 3.0

DMA Request1:Pin 3.1

DMA request signal

Associated peripheral

function

DMA trigger

0

USB RX

USB correct transfer event

1

USB TX

2TIM0

Input Capture and Output Compare

events

3TIM1

4UART0 RX

FIFO watermark level reached

5UART0 TX

6UART1RX

7

UART1TX

8

External DMA Req0

Rising edge of P3.0

9

External DMA Req1

Rising edge of P3.1

10

-

Reserved

11

-