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LT1722/LT1723/LT1724

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The LT1722/LT1723/LT1724 may be inserted directly into

many operational ampliﬁer applications improving both DC

and AC performance, as well as noise and distortion.

Layout and Passive Components

The LT1722/LT1723/LT1724 ampliﬁers are more tolerant

of less than ideal layouts than other high speed ampliﬁers.

For maximum performance (for example, fast settling time)

use a ground plane, short lead lengths and RF quality

bypass capacitors (0.01μF to 0.1μF). For high drive current

applications, use low ESR supply bypass capacitors (1μF

to 10μF tantalum). The output/input parasitic coupling

should be minimized when high frequency performance

is required.

The parallel combination of the feedback resistor and gain

setting resistor on the inverting input combine with the

input capacitance to form a pole that can cause peaking

or even oscillations. In parallel with the feedback resistor,

a capacitor of value:

CF > RG • CIN/RF

should be used to cancel the input pole and optimize

dynamic performance. For unity-gain applications where

a feedback resistor is used, such as an I-to-V converter,

CF should be ﬁve times greater than CIN; an optimum

value for CF is 10pF.

Input Considerations

Each of the LT1722/LT1723/LT1724 inputs is protected with

back-to-back diodes across the bases of the NPN input

devices. If greater than 0.7V differential input voltages are

anticipated, the input current must be limited to less than

10mA with an external series resistor. Each input also has

two ESD clamp diodes—one to each supply. If an input is

driven beyond the supply, limit the current with an external

resistor to less than 10mA. The input stage protection

circuit is shown in Figure 1.

The input currents of the LT1722/LT1723/LT1724 are

typically in the tens of nA range due to the bias current

cancellation technique used at the input. As the input

offset current can be greater than either input current,

APPLICATIONS INFORMATION

Figure 1. Input Stage Protection

adding resistance to balance source resistance is not

recommended. The value of the source resistor should

be below 12k as it actually degrades DC accuracy and

also increases noise.

Total Input Noise

The total input noise of the LT1722/LT1723/LT1724 is

optimized for a source resistance between 0.8k and 12k.

Within this range, the total input noise is dominated by

the noise of the source resistance itself. When the source

resistance is below 0.8k, voltage noise of the ampliﬁer

dominates. When the source resistance is above 12k, the

input noise current is the dominant contributor.

Capacitive Loading

The LT1722/LT1723/LT1724 drive capacitive loads up to

100pF with unity gain. As the capacitive load increases,

both the bandwidth and the phase margin decrease causing

peaking in the frequency response and overshoot in the

transient response. When there is a need to drive a larger

capacitive load, a 25Ω series resistance assures stability

with any value of load capacitor. A feedback capacitor also

helps to reduce any peaking.

Power Dissipation

The LT1722/LT1723/LT1724 combine high speed and

large output drive in a small package. Maximum junction

temperature(TJ)iscalculatedfromtheambienttemperature

(TA), power dissipation per ampliﬁer (PD) and number of

ampliﬁers (n) as follows:

TJ = TA + (n • PD • θJA)

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