AN2645 datasheet(34/36 Pages) STMICROELECTRONICS

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Block-by-block compatibility analysis

AN2645

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3.7.8

Option bytes

As the block of option bytes is placed in the last page of EEPROM data memory its position

varies in address space.

The basic structure of the option byte area is compatible across the family. There are some

differences in the actual settings and option bit meanings between sub-families.

The first difference is in the OPT1 option bits setting which controls the User Boot Code

(UBC) protected area. The settings differ due to the different page sizes in each sub-family

which are described in Section 3.7.1: Flash program memory on page 30. Some settings

are reserved depending on the size the FLASH program memory and in some cases the

same code can correspond to a different number of pages in some sub-families.

The next difference is in the OPT2 option bits settings which enable the alternate option

functions for the GPIOs. The option bits of this register have the same meaning for the

STM8S208x, 207x and 105x sub-families, but they differ for the STM8S103x sub-family and

differ again for the STM8S903x sub-family. For STM8S103x these bits are divided into two

groups. Bits 6,5,1 and 0 are for the STM8S103K (32-pin device) and bits 7,5.4 and 3 are for

STM8S103F (20-pin device).

In the OPT3 option, the HSITRIM bit is present in Access line but not in Performance line

devices. This bit controls the number of calibration steps when the HSI clock frequency is

trimmed (see Section 3.6.2: HSI clock frequency).

The OPT5 register settings differ between Access and Performance line. Optional HSE

oscillator stabilization time has two times higher numbers of clock periods for Performance

line.

The OPT7 register (FLASH memory access wait states) settings is used only in the STM8S

Performance line family.

The OPTBL optional switching the reset vector to the boot loader area is not available for the

103x sub-family where any boot loader area memory is not present.

ADC1/

ADC2

0x8060

ADC2 End of

conversion

interrupt

ADC1 End of

conversion/Analog

watchdog

interrupts

ADC1 End of

conversion/Analog

watchdog

interrupts

ADC1 End of

conversion/Analog

watchdog

interrupts

TIM4/TIM6

0x8064

TIM4

Update/Overflow

TIM4

Update/Overflow

TIM4

Update/Overflow

TIM6

Update/Overflow/

Trigger

Table 30.

Interrupt vector table differences (continued)

Priority

Source

block

Interrupt

vector

address

STM8S208x

STM8S207x

STM8S105x

STM8S103x

STM8S903x

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