Interfacing with an 8-bit NAND Flash memory

AN2784

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Doc ID 14779 Rev 4

Figure 11 illustrates a typical connection between the STM32F10xxx microcontroller and the

NAND512W3A memory. It is an abstract from the schematic of the STM32F10xxx

evaluation board: STM3210E-EVAL.

Figure 11.

8-bit NAND Flash: NAND512W3A2C/NAND512W3A2B connection to

STM32F10xxx

A firmware example is available within the STM32F10xxx firmware library provided in the

NAND directory at the path:

STM32F10x_StdPeriph_Lib\Project\STM32F10x_StdPeriph_Examples\FSMC.

The main goal of this example is to provide the basics of how to use the FSMC firmware

library and the associated NAND Flash memory driver to perform erase/read/write

operations using the FSMC wait feature on the NAND512W3A2 memory mounted on the

STM3210E-EVAL board.

4.4

Error correction code computation

4.4.1

Error correction code (ECC) computation overview

The FSMC NAND Flash controller includes two pieces of error correction code computation

hardware, one for each NAND Flash memory block.

The ECC can be performed for page sizes of 256, 512, 1024, 2048, 4096 or 8192 bytes,

size, the ECC code will be 22, 24, 26, 28, 30 or 32 bits.

To even improve the error coverage, the user can read/write the NAND Flash page with a

reduced ECC page size. This is possible when starting and stopping the ECC computation

after the desired number of bytes to check. In this case, the ECC code is only calculated for

the bytes written and read.

RB

7

R

8

E

9

VDD

12

VSS

13

CL

16

AL

17

W

18

WP

19

I/O0

29

I/O1

30

I/O2

31

I/O3

32

VSS

36

VDD

37

I/O4

41

I/O5

42

I/O6

43

I/O7

44

U3

NAND512W3A2CN6E

+3V3

A16

A17

FSMC_NCE2

FSMC_NWE

FSMC_NOE

FSMC_NWAIT

1

2

3

JP1

C3

100nF

C1

100nF

R3

10K

+3V3

C2

100nF

R1

10K

+3V3

R5

10K

+3V3

D0

D1

D2

D3

D4

D5

D6

D7

R2

10K

R4

do not fit

Default setting: 2<->3

NAND512W3A2BN6E

PD6

PD4

PD7

PG6

FSMC_INT2

PD14

PD15

PD0

PD1

PE7

PE8

PE9

PE10

PD11

PD12

PD5

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