UPD703003 datasheet(50/82 Pages) NEC

50 / 82 page

µPD703003

Data Sheet U12261EJ2V1DS00

Instruction Mnemonic

Operand

Opcode

Operation

Flags

group

CY OV SZ SAT

Arithmetic MULH

reg1, reg2

r r r r r 0 0 0 1 1 1 RRRRR GR[reg2]

← GR[reg2]Note × GR[reg1]Note

operation

(signed multiplication)

instructions

MULH

imm5, reg2

rr r r r 0 1 0 1 1 1 i i i i i

GR[reg2]

← GR[reg2]Note × sign-extend (imm5)

(signed multiplication)

MULHI

imm16, reg1, reg2

r r r r r 1 1 0 1 1 1 RRRRR GR[reg2]

← GR[reg1]Note × imm16

ii iii iii iii iii i i

(signed multiplication)

DIVH

reg1, reg2

r r r r r 0 0 0 0 1 0 RRRRR GR[reg2]

← GR[reg2] ÷ GR[reg1]Note (signed division)

×× ×

CMP

reg1, reg2

r r r r r 0 0 1 1 1 1 RRRRR result

← GR[reg2] – GR[reg1]

×× × ×

CMP

imm5, reg2

rr r r r 0 1 0 0 1 1 i i i i i

result

← GR[reg2] – sign-extend (imm5)

×× × ×

SETF

cccc, reg2

r r r r r 1 1 1 1 1 1 0cc c c if conditions are satisfied

00 000 0 00 000 0 00 00

then GR[reg2]

← 00000001H

else GR[reg2]

← 00000000H

Saturated SATADD reg1, reg2

r r r r r 0 0 0 1 1 0 RRRRR GR[reg2]

← saturated (GR[reg2] + GR[reg1])

× × ×××

operation

SATADD imm5, reg2

r r r r r 0 1 0 0 0 1 i i i i i

GR[reg2]

← saturated (GR[reg2] + sign-extend (imm5)) × × ×××

instructions

SATSUB reg1, reg2

r r r r r 0 0 0 1 0 1 RRRRR GR[reg2]

← saturated (GR[reg2] – GR[reg1])

× × ×××

SATSUBI imm16, reg1, reg2

r r r r r 1 1 0 0 1 1 RRRRR GR[reg2]

← saturated (GR[reg1] – sign-extend (imm16)) × × ×××

ii iii iii iii iii i i

SATSUBR reg1, reg2

r r r r r 0 0 0 1 0 0 RRRRR GR[reg2]

← saturated (GR[reg1] – GR[reg2])

× × ×××

Logical

TST

reg1, reg2

r r r r r 0 0 1 0 1 1 RRRRR result

← GR[reg2]AND GR[reg1]

××

operation

reg1, reg2

r r r r r 0 0 1 0 0 0 RRRRR GR[reg2]

← GR[reg2]OR GR[reg1]

××

instruction

ORI

imm16, reg1, reg2

r r r r r 1 1 0 1 0 0 RRRRR GR[reg2]

← GR[reg1]OR zero-extend (imm16)

××

ii iii iii iii iii i i

AND

reg1, reg2

r r r r r 0 0 1 0 1 0 RRRRR GR[reg2]

← GR[reg2]AND GR[reg1]

××

ANDI

imm16, reg1, reg2

r r r r r 1 1 0 1 1 0 RRRRR GR[reg2]

← GR[reg1]AND zero-extend (imm16)

0 0

ii iii iii iii iii i i

XOR

reg1, reg2

r r r r r 0 0 1 0 0 1 RRRRR GR[reg2]

← GR[reg2]XOR GR[reg1]

××

XORI

imm16, reg1, reg2

r r r r r 1 1 0 1 0 1 RRRRR GR[reg2]

← GR[reg1]XOR zero-extend (imm16)

××

ii iii iii iii iii i i

NOT

reg1, reg2

rr r r r 0 0 0 0 1 RRRRR

GR[reg2]

← NOT (GR[reg1])

××

SHL

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

← GR[reg2]logically shift left by GR[reg1]

× 0 ××

00 000 0 00 110 0 00 00

SHL

imm5, reg2

rr r r r 0 1 0 1 1 0 i i i i i

GR[reg2]

← GR[reg2]logically shift left by

× 0 ××

zero-extend (imm5)

SHR

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

← GR[reg2]logically shift right by GR[reg1] × 0 ××

00 000 0 00 100 0 00 00

SHR

imm5, reg2

rr r r r 0 1 0 1 0 0 i i i i i

GR[reg2]

← GR[reg2]logically shift right by

× 0 ××

zero-extend (imm5)

SAR

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

← GR[reg2]arithmetically shift right by

× 0 ××

00 000 0 00 101 0 00 00

GR[reg1]

SAR

imm5, reg2

rr r r r 0 1 0 1 0 1 i i i i i

GR[reg2]

← GR[reg2]arithmetically shift right by

× 0 ××

zero-extend (imm5)

Note Only the low-order half word is valid.

UPD703003 Datasheet(PDF) 50 Page - NEC

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