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AN3961 Datasheet(PDF) 25 Page - STMicroelectronics |
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AN3961 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 46 page ![]() DocID022083 Rev 3 25/46 AN3961 Hardware layout and configuration 46 Figure 13. Acquisition by program “3” Table 12. Program “4” Five level - HV1=±40 V, HV0=±80 V; Load: 300 pF//100 Ω Mode Time width per level Number of pulses Initial pulse PRF ChA 5 level 1.5 cycle, 200 ns per level @ ±80 V +4 cycles, 100 ns per level @ 40 V 1.5+4 Positive 150 µs ChB 5 level 1.5 cycle, 200 ns per level @ ±80 V +4 cycles, 100 ns per level @ 40 V 1.5+4 Negative 150 µs ChC 5 level 1.5 cycle, 100 ns per level @ ±80 V +4 cycles, 100 ns per level @ 40 V 1.5+4 Positive 150 µs ChD 5 level 1.5 cycle, 100 ns per level @ ±80 V +4 cycles, 100 ns per level @ 40 V 1.5+4 Negative 150 µs |
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