Recommendations when developing the M24LRxxE_R application software

AN4125

12/15

Doc ID 023297 Rev 1

Application hardware architecture

The application Master should control the I²C bus lines and the power supply line so as to

keep full control of the M24LRxxE_R. Figure 10 shows a typical hardware schematic.

Figure 10.

Optimal hardware schematic of an M24LRxxE_R application

This type of hardware architecture is optimal in applications where power saving is a key

feature (like portable applications supplied from a battery). The supply voltage can be

directly delivered to an ultralow power microcontroller (for instance the STM8L, information

available from http://www.st.com/mcu/). This implementation makes it possible to keep the

application supply current in the 1 µA range (value of the STM8L supply current when in the

Active-Alt mode) and:

●

the application saves power when in the Standby mode, as the battery does not supply

the standby current to the M24LRxxE_R (40 µA) nor the current through the SDA pull-

up resistor

●

the Master only when an I²C request is being processed)

2.1.3

An I²C request was interrupted

A Start condition defines the I²C channel as busy until the completion of the I²C command

(Stop condition) or until I²C timeout. If for some uncontrolled reason, inadvertent

unterminated instructions are sent to the I²C bus, the M24LRxxE-R features a timeout

mechanism that automatically resets the I²C logic block.

The I²C busy state is reset either:

●

by decoding a device select byte different from 1010 XXXXb,

●

by decoding a Stop condition,

●

instruction), or

●

after timeout.

The best way for the I²C bus Master to clear a spurious busy state is to periodically issue a

[Start+Stop] sequence.

Note:

In noisy applications, ST recommends to implement the “9 Start + 1 Stop” sequence

described in AN1471 (available from the ST website: www.st.com).

M24LRxxE-R