AN4157

Peripheral firmware examples description

Doc ID 023629 Rev 1

11/24

3.10

IWDG reset example

3.10.1

Purpose

This example shows how to update the IWDG reload counter at regular periods, and how to

simulate a software fault by generating an MCU IWDG reset when the programmed time

period has expired.

3.10.2

Description

In this example:

●

The independent watchdog timeout is set to 250 ms.

●

The SysTick timer is configured to generate an interrupt every 250 ms.

●

In the SysTick interrupt service routine, the independent watchdog counter is reloaded

to prevent an independent watchdog reset, and LED4 is toggled.

●

The EXTI line 0 connected to PA0 pin is configured to generate an interrupt on its falling

edge.

●

In the NVIC, the EXTI line 0 corresponding interrupt vector is enabled with a priority

equal to 0, and the systick interrupt vector priority is set to 1 (EXTI interrupt occurs prior

to systick interrupt).

●

The EXTI line is used to simulate a firmware failure: when the EXTI line event is

triggered (after pressing the user push-button on the STM32F3DISCOVERY board),

the corresponding interrupt is serviced. In the ISR, LED3 is switched off and the EXTI

line pending bit is not cleared. The CPU executes the EXTI line ISR indefinitely and the

SysTick interrupt routine is never entered, so the independent watchdog counter is not

reloaded. As a result, when the independent watchdog counter reaches 00, the

independent watchdog generates a reset.

When the program is running and the independent watchdog reset is generated, LED3 is

turned on after the system resumes operation.

3.11

OPMAP in programmable gain amplifier example

3.11.1

Purpose

This example shows how to configure OPAMP1 peripheral to amplify a signal applied to

OPAMP1 non inverting input using the built-in PGA.

3.11.2

Description

In this example, OPAMP1 is configured as following:

●

PGA mode enabled with gain set to 2

●

Non Inverting input is connected to PA5

●

Output is available on PA2