1999

IEEE1394 OHCI HOST CONTROLLER

DATA SHEET

MOS INTEGRATED CIRCUIT

Document No. S14265EJ2V0DS00 (2nd edition)

Date Published December 1999 NS CP (K)

Printed in Japan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

The

µPD72862 is IEEE1394 OHCI-Link controller. The µPD72862 complies with the P1394a draft 2.0

specifications and works up to 400 Mbps.

It supports both of the Cardbus interface and the PCI bus interface.

FEATURES

• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0

• Compliant with protocol enhancement as defined in P1394a draft 2.0

• Modular 32-bit host interface compliant to PCI Specification release 2.1

• Supports PCI-Bus Power Management Interface Specification release 1.0

• Supports Cardbus

• Equipped CIS register

• Cycle Master and Isochronous Resource Manager capable

• Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface

• Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048

bytes)

• 32-bit CRC generation and checking for receive/transmit packets

• 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported

• Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY

• Internal control and operational registers direct-mapped to PCI configuration space

ORDERING INFORMATION

Part number

Package

µPD72862GC-9EU

100-pin plastic TQFP (Fine pitch) (14 x 14)

The mark 5

5

5

5 shows major revised points.