DocID027161 Rev 1

13/26

AN4617

Peripheral migration

25

User can use the clock configuration tool (STM32xxxx_Clock_Configuration.xls), to

generate a customized system_stm32xxxx.c file containing a system clock configuration

routine, depending on the application requirements.

Concerning the peripheral access configuration user has to check mapping of the

peripherals’ registers and adapt their control of reset and clock gating at proper AHBx and

APBx registers at RCC (xxxxRSTR & xxxxENR) refer to Table 5. L0 series feature additional

control of clock gating at sleep mode (xxxxSMENR).

When configuring peripheral clock sources to a dedicated clock source independent from

the system clock, the source has to be checked during migration because of differences

summarized inTable 7.

2.5

DMA interface

Both STM32F0 and STM32L0 series feature up to 7-channel DMA controller. Some devices

(e.g. STM32F09x) feature 5 additional independently configurable channels on DMA2. Each

channel is dedicated to managing memory access requests from one or more peripherals.

The difference lies in optional remapping of DMA requests. While for F0 it is performed by

specific bits at SYSCFG_CFGR1 configuration register, in L0 we have specific channel

selection registers (CSELR).

Table 8 shows the basic differences between the DMA1 requests of peripherals among the

STM32F0 and STM32L0 series.

Table 7. Possible configuration of IPs’ clock sources

Peripheral

STM32F0 series

STM32L0 series

ADC

HSI14, PCLK divided by 2 or by 4

HSI16 or HSI16/4 with prescaler,

PCLK divided by 1, 2 or 4

USB

HSI48, PLL

HSI48, PLL VCO

USART

system clock, HSI8, LSE, APB

system clock, HSI16, LSE, APB

I2C

system clock, HSI8

system clock, HSI16, APB

RTC

LSE, LSI (40 kHz),

HSE (divided by 32)

LSE, LSI (38 kHz),

HSE_RTC (programmable prescaler)