Specifications GAL6002

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Array Description

an AND array and the second is an OR array. These arrays are de-

scribed in detail below.

AND ARRAY

The AND array is organized as 78 inputs by 75 product term outputs.

The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC feed-

backs, and ICLK comprise the 39 inputs to this array (each available

in true and complement forms). 64 product terms serve as inputs

to the OR array. The RESET product term generates the RESET

signal described in the Output and Buried Logic Macrocells sec-

tion. There are 10 output enable product terms which allow device

I/O pins to be bi-directional or tri-state.

OR ARRAY

The OR array is organized as 64 inputs by 36 sum term outputs.

64 product terms from the AND array serve as the inputs to the OR

array. Of the 36 sum term outputs, 18 are data (“D”) terms and 18

are enable/clock (“E”) terms. These terms feed into the 10 OLMCs

and 8 BLMCs, one “D” term and one “E” term to each.

The programmable OR array offers unparalleled versatility in prod-

uct term usage. This programmability allows from 1 to 64 product

terms to be connected to a single sum term. A programmable OR

array is more flexible than a fixed, shared, or variable product term

architecture.

Electronic Signature

An electronic signature is provided with every GAL6002 device. It

contains 72 bits of reprogrammable memory that can contain user

defined data. Some uses include user ID codes, revision numbers,

or inventory control. The signature data is always available to the

user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula-

tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided with every GAL6002 device as a deterrent

to unauthorized copying of the array patterns. Once programmed,

this cell prevents further read access to the AND array. This cell

can be erased only during a bulk erase cycle, so the original con-

figuration can never be examined once this cell is programmed.

The Electronic Signature is always available to the user, regard-

less of the state of this control cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-

approved Logic Programmer, available from a number of manufac-

turers. Complete programming of the device takes only a few

seconds. Erasing of the device is transparent to the user, and is

done automatically as part of the programming cycle.

Typical Input Pull-up Characteristic

1. 0

2 . 0

3. 0

4 . 0

5. 0

-6 0

0

-2 0

-4 0

0

Input V o lt ag e ( V olt s)

Register Preload

When testing state machine designs, all possible states and state

transitions must be verified, not just those required during normal

operations. This is because certain events may occur during sys-

tem operation that cause the logic to be in an illegal state (power-

up, line voltage glitches, brown-out, etc.). To test a design for proper

treatment of these conditions, a method must be provided to break

the feedback paths and force any desired state (i.e., illegal) into the

registers. Then the machine can be sequenced and the outputs

tested for correct next state generation.

All of the registers in the GAL6002 can be preloaded, including the

ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con-

tents of the state and output registers can be examined in a special

diagnostics mode. Programming hardware takes care of all preload

timing and voltage requirements.

Latch-Up Protection

GAL6002 devices are designed with an on-board charge pump to

negatively bias the substrate. The negative bias is of sufficient

magnitude to prevent input undershoots from causing the circuitry

to latch. Additionally, outputs are designed with n-channel pull-ups

instead of the traditional p-channel pull-ups to eliminate any pos-

sibility of SCR induced latching.

Input Buffers

GAL6002 devices are designed with TTL level compatible input

buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

devices.

GAL6002 input buffers have active pull-ups within their input struc-

ture. This pull-up will cause any un-terminated input or I/O to float

to a TTL high (logical 1). Lattice Semiconductor recommends that

all unused inputs and tri-stated I/O pins be connected to another

active input, Vcc, or GND. Doing this will tend to improve noise

immunity and reduce Icc for the device.