UPD75106 datasheet(21/70 Pages) NEC

21 / 70 page

µPD75104, 75106, 75108

5.2

CLOCK GENERATOR CIRCUIT

The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and

peripheral hardware. In addition, this circuit can change the instruction execution time.

• 0.95

µs/1.91 µs/15.3 µs (operating at 4.19 MHz)

· Basic interval timer (BT)

· Clock output circuit

· Timer/event counter

· Serial interface

f X

1/2 1/16

1/8 to 1/4096

Frequency civider

System clock

generator

circuit

Oscillation

stops

1/4

Frequency

divider

· CPU

· Clock output

circuit

HALT F/F

PCC

PCC0

PCC1

PCC2

PCC3

HALT*

STOP*

Clears

PCC2,

PCC3

STOP F/F

Wait release signal from BT

RES (internal reset) signal

Standby release signal from

interrupt control circuit

*: Execution of the instruction

Remarks 1: fXX= Crystal/ceramic oscillator

2: fX = External clock frequency

3: PCC: Processor clock control register

4: One clock cycle (tCY) of

Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 12. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

UPD75106 Datasheet(PDF) 21 Page - NEC

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