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UPD75112FGF Datasheet(PDF) 12 Page - NEC |
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UPD75112FGF Datasheet(HTML) 12 Page - NEC |
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12 / 78 page ![]() 12 µPD75108F,75112F,75116F 3.5 PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test mode for testing internal µPD75116F operation (for IC testing). The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if noise exceeding VDD is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. If, for example, inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from these pins, and the pin voltage exceeds VDD, misoperation may result. Wiring should therefore be carried out so that interwiring noise is suppressed as far as possible. If it is completely impossible to suppress noise, noise prevention measures should be taken using an external component as shown below. q q Capacitor connected between P00/INT4 or RESET and VDD q q Diode with small VF (0.3 V or less) connected between P00/INT4 or RESET and VDD VDD VDD P00/INT4, RESET Diode with small VF VDD VDD P00/INT4, RESET |
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