UPD753206 datasheet(39/80 Pages) NEC

39 / 80 page

µPD753204, 753206, 753208

Table 9-1. Status of Each Device After Reset (1/2)

Hardware

RESET signal generation

in the standby mode

during operation

Program counter (PC)

µPD753204 Sets the low-order 4 bits of

Sets the low-order 4 bits of

program memory’s address

0000H to PC11 to PC8 and

the contents of address 0001H

to PC7 to PC0.

µPD753206, Sets the low-order 5 bits of

Sets the low-order 5 bits of

µPD753208 program memory's address

program memory's address

0000H to PC12 to PC8 and

the contents of address 0001H

to PC7 to PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0-SK2)

Interrupt status flag (IST0, IST1)

Bank enable flag (MBE, RBE)

Sets bit 6 of program memory’s

address 0000H to RBE and bit

7 to MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

1000B

Data memory (RAM)

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Held

Undefined

Bank select register (MBS, RBS)

0, 0

Basic interval

Counter (BT)

Undefined

timer/watchdog

Mode register (BTM)

timer

Watchdog timer enable flag (WDTM)

Timer/event

Counter (T0)

counter (T0)

Modulo register (TMOD0)

FFH

Mode register (TM0)

TOE0, TOUT F/F

0, 0

Timer

Counter (T1)

counter (T1)

Modulo register (TMOD1)

FFH

Mode register (TM1)

TOE1, TOUT F/F

0, 0

Timer

Counter (T2)

counter (T2)

Modulo register (TMOD2)

FFH

High-level period setting modulo

FFH

Mode register (TM2)

TOE2, TOUT F/F

0, 0

REMC, NRZ, NRZB

0, 0, 0

TGCE

Watch timer

Mode register (WM)

UPD753206 Datasheet(PDF) 39 Page - NEC

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