LT1508CSW datasheet(11/16 Pages) LINER

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LT1508

APPLICATIONS INFORMATION

input up to VC and then the SS2 voltage continues beyond

VC. The PWMOK comparator contains hysteresis and will

pull SS2 low disabling the PWM section if the PFC output

voltage falls below approximately 62% of its preset value

(240V with nominal 382V output).

Start-Up and Supply Voltage

The LT1508 draws only 250

µA before the chip starts at

16V on VCC. To trickle start, a 91k resistor from the power

line to VCC supplies trickle current, and C4 holds VCC up

while switching starts (see Figure 8); then the auxiliary

winding takes over and supplies the operating current.

Note that D3 and the larger values of C3 are only necessary

for systems that have sudden large load variations down

to minimum load and/or very light load conditions. Under

these conditions the loop may exhibit a start/restart mode

because switching remains off long enough for C4 to

discharge below 10V. Large values for C3 will hold VCC up

until switching resumes. For less severe load variations D3

is replaced with a short and C3 is omitted. The turns ratio

between the primary winding determines VCC

according to :

VOUT

VCC – 2V

for 382V VOUT and 18V VCC, Np/Ns ≈ 19.

Figure 8

VCC

91k

µF

1508 • F08

µF

390

µF

100

µF

LINE

MAIN INDUCTOR

Output Capacitor (PFC Section)

GTDR2 (PWM) pulse is synchronized to GTDR1 (PFC) pulse

with 53% duty cycle delay to reduce RMS ripple current in the

output capacitor. See PFC/PWM Synchronization graph in

the Typical Performance Characteristics section.

The peak-to-peak 120Hz PFC output ripple is determined by:

VP-P = 2ILOAD(DC)(Z)

where ILOAD(DC) is the DC load current of the PWM stage

and Z is the capacitor impedance at 120Hz.

For 470

µF, impedance is 2.8Ω at 120Hz. At 335W load,

ILOAD(DC) = 335V/382V = 0.88A, VP-P = (2)(0.88)(2.8Ω) =

5V. If less ripple is desired higher capacitance should be

used. The selection of the output capacitor is based on

voltage ripple, hold-up time and ripple current. Assuming

the DC converter (PWM section) is designed to operate

with 240V to 382VIN , the minimum hold-up time is a

function of the energy storage capacity of the capacitor:

(0.5)COUT

POUT

tHOLD =

(382V – 0.5VP–P)2 – 240V2

with COUT = 470µF, VP-P = 11.5V, and POUT = 335W,

tHOLD = 60ms which is 3.6 line cycles at 60Hz. The ripple

current can be divided into two major components. The

first is the 120Hz component which is related to the DC

load current as follows:

I120HZ ≈ ILOAD(DC) 2

√

The second component is made up of switching frequency

components due to the PFC stage charging the capacitor

and the PWM stage discharging the capacitor. For a 300W

output PFC forward converter running from an input

voltage of 100VRMS, the total high frequency ripple current

was measured to be 1.79ARMS.

For the United Chemicon KMH 450V capacitor series,

ripple current at 100kHz is specified 1.43 times higher

than the 120Hz limit.

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