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LT1776

TIMING DIAGRAMS

Low dV/dt Mode

High dV/dt Mode

SWOFF

1776 TD02

BOOST

SWON

SWDR

VIN

VSW

SWOFF

1776 TD01

BOOST

SWON

SWDR

VIN

VSW

The LT1776 is a current mode switching regulator IC that

has been optimized for high efficiency operation in high

input voltage, low output voltage buck topologies. The

Block Diagram shows an overall view of the system.

Several of the blocks are straightforward and similar to

those found in traditional designs, including: Internal Bias

Regulator, Oscillator and Feedback Amplifier. The novel

portion includes an elaborate Output Switch section and

Logic Section to provide the control signals required by

the switch section.

The LT1776 operates much the same as traditional

current mode switchers, the major difference being its

specialized output switch section. Due to space con-

straints, this discussion will not reiterate the basics of

current mode switcher/controllers and the “buck” topol-

ogy. A good source of information on these topics is

Application Note 19.

Output Switch Theory

One of the classic problems in delivering low output

voltage from high input voltage at good efficiency is that

minimizing AC switching losses requires very fast volt-

age (dV/dt) and current (dI/dt) transition at the output

device. This is in spite of the fact that in a bipolar

implementation, slow lateral PNPs must be included in

the switching signal path.

OPERATIO

Fast positive-going slew rate action is provided by lateral

PNP Q3 driving the Darlington arrangement of Q1 and Q2.

The extra

β available from Q2 greatly reduces the drive

requirements of Q3.

Although desirable for dynamic reasons, this topology

alone will yield a large DC forward voltage drop. A second

lateral PNP, Q4, acts directly on the base of Q1 to reduce

the voltage drop after the slewing phase has taken place.

To achieve the desired high slew rate, PNPs Q3 and Q4 are

“force-fed” packets of charge via the current sources

controlled by the boost signal.

Please refer to the High dV/dt Mode Timing Diagram. A

typical oscillator cycle is as follows: The logic section first

generates an SWDR signal that powers up the current

comparator and allows it time to settle. About 1

µslater,the

SWON signal is asserted and the BOOST signal is pulsed

for a few hundred nanoseconds. After a short delay, the

VSW pin slews rapidly to VIN. Later, after the peak switch

current indicated by the control voltage VC has been

reached (current mode control), the SWON and SWDR

signals are turned off, and SWOFF is pulsed for several

hundred nanoseconds. The use of an explicit turn-off

device, i.e., Q5, improves turn-off response time and thus

aids both controllability and efficiency.

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