UPD754244GS datasheet(65/88 Pages) NEC

65 / 88 page

µPD754144, 754244

•

µPD754244

Interrupt Input Timing

RESET Input Timing

Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = –40 to +85

°C)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

tSREL

µs

Oscillation stabilization

tWAIT

Release by RESET

Note 2

wait time Note 1

Release by interrupt request

Note 3

Notes 1.

The oscillation stabilization wait time is the time during which the CPU operation is stopped to

avoid unstable operation at oscillation start.

217/fx and 215/fx can be selected with mask option.

Depends on setting of basic interval timer mode register (BTM) (see table below).

BTM3

BTM2

BTM1

BTM0

Wait Time

When fX = 4.19 MHz

When fX = 6.0 MHz

–00

220/fX (Approx. 250 ms)

220/fX (Approx. 175 ms)

–01

217/fX (Approx. 31.3 ms)

217/fX (Approx. 21.8 ms)

–10

215/fX (Approx. 7.81 ms)

215/fX (Approx. 5.46 ms)

–11

213/fX (Approx. 1.95 ms)

213/fX (Approx. 1.37 ms)

RESET

tRSL

INT0, KR4 to KR7

tINTL

tINTH

UPD754244GS Datasheet(PDF) 65 Page - NEC

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