LTC1283CS datasheet(11/24 Pages) LINER

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LTC1283

1 ACLK cycle. After a change of state on the CS input, the

LTC1283 waits for two falling edges of the ACLK before

recognizing a valid chip select. One indication of CS low

recognition is the DOUT line becoming active (leaving the

Hi-Z state). Note that the deglitching applies to both the

rising and falling CS edges.

MSB-First/LSB-First Format (MSBF)

The output data of the LTC1283 is programmed for MSB-

first or LSB-first sequence using the MSBF bit. For MSB-

first output data the input word clocked to the LTC1283

should always contain a logical one in the sixth bit location

(MSBF bit). Likewise for LSB-first output data, the input

word clocked to the LTC1283 should always contain a zero

in the MSBF bit location. The MSBF bit in a given DIN word

will control the order of the next DOUT word. The MSBF bit

affects only the order of the output data word. The order

of the input word is unaffected by this bit.

APPLICATI

I FOR ATIO

MSBF

OUTPUT FORMAT

LSB-First

MSB-First

LTC1283 AI08

Figure 2 shows how the data output (DOUT) timing can be

controlled with word length selection and MSB/LSB-first

format selection.

3. Deglitcher

A deglitching circuit has been added to the chip select

input of the LTC1283 to minimize the effects of errors

caused by noise on that input. This circuit ignores changes

in state on the CS input that are shorter in duration than

4. CS Low During Conversion

In the normal mode of operation, CS is brought high

during the conversion time (see Figure 3). The serial port

ignores any SCLK activity while CS is high. The LTC1283

will also operate with CS low during the conversion. In this

mode, SCLK must remain low during the conversion as

shown in Figure 4. After the conversion is complete, the

DOUT line will become active with the first output bit. Then

the data transfer can begin as normal.

5. Microprocessor Interfaces

The LTC1283 can interface directly (without external hard-

ware) to most popular microprocessor (MPU) synchro-

nous serial formats (see Table 2). If an MPU without a

serial interface is used, then four of the MPU’s parallel port

lines can be programmed to form the serial link to the

LTC1283. Included here are three serial interface ex-

amples and one example showing a parallel port pro-

grammed to form the serial interface.

Word Length (WL1, WL0)

The last two bits of the input word (WL1 and WL0)

program the output data word length of the LTC1283.

Word lengths of 8-, 10-, 12- or 16-bit can be selected

according to the following table. The WL1 and WL0 bits in

a given DIN word control the length of the present, not the

next, DOUT word. WL1 and WL2 are never “don’t cares”

and must be set for the correct DOUT word length even

when a “dummy” DIN word is sent. On any transfer cycle,

the word length should be made equal to the number of

SCLK cycles sent by the MPU.

WL1

OUTPUT WORD LENGTH

8 Bits

10 Bits

12 Bits

16 Bits

LTC1283 • AI09

WL0

ACLK

DOUT

HI-Z

VALID OUTPUT

ACLK

DOUT

VALID OUTPUT

LTC1283 • AI10

HI-Z

LOW CS RECOGINZED INTERNALLY

HIGH CS RECOGNIZED INTERNALLY

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