 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC1400CS8 Datasheet(PDF) 11 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LTC1400CS8 Datasheet(HTML) 11 Page - Linear Technology |
|
|
11 / 20 page  11 LTC1400 APPLICATIONS INFORMATION error adjustment. Figure 10b shows offset and full-scale adjustment. Offset error must be adjusted before full- scale error. Zero offset is achieved by applying 0.5mV (i.e., 0.5LSB) at the input and adjusting the offset trim until the LTC1400 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 4.0945V (FS – 1.5LSB or last code transi- tion) at the input and adjust R5 until the LTC1400 output code flickers between 1111 1111 1110 and 1111 1111 1111. Bipolar Offset and Full-Scale Error Adjustments Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Bipolar offset error adjust- ment is achieved by applying an input voltage of – 0.5mV (– 0.5LSB) to the input in Figure 10c and adjusting the op amp until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.0465V (FS – 1.5LSBs) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1400, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by GND. High quality tantalum and ceramic bypass capacitors should be used at the VCC and VREF pins as shown in the Typical Application on the first page of this data sheet. For the bipolar mode, a 0.1 µF ceramic provides adequate bypassing for the VSS pin. For optimum performance, a 10 µF surface mount AVX capacitor with a 0.1µF ceramic is recommended for the VCC and VREF pins. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. In unipolar mode operation, VSS should be isolated from any noise source before shorting to the GND pin. LTC1400 • F10a – + R2 10k R3 10k R1 50 Ω R4 100 Ω FULL-SCALE ADJUST VIN A1 LTC1400 AIN GND ADDITIONAL PINS OMITTED FOR CLARITY ±20LSB TRIM RANGE Figure 10a. LTC1400 Full-Scale Adjust Circuit LTC1400 • F10b – + R2 10k R9 20 Ω R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R6 400 Ω R1 10k 10k ANALOG INPUT 0V TO 4.096V A1 5V R8 10k OFFSET ADJUST R7 100k 5V AIN LTC1400 Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit LTC1400 • F10c – + R2 10k R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R6 200 Ω R1 10k ANALOG INPUT ±2.048V A1 R8 20k OFFSET ADJUST R7 100k 5V –5V AIN LTC1400 Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
