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LTC1436A

LTC1436A-PLL/LTC1437A

APPLICATIONS INFORMATION

The power dissipation on the topside MOSFET can be

easily estimated. Choosing a Siliconix Si4412DY results

in: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input

voltage with T (estimated) = 50

°C:

kHz

MAIN =

() +() °− °

()

[]()

() ( )(

)(

) =

0 005 50

0 042

2 5 22

100

250

185

Ω

The most stringent requirement for the synchronous

N-channel MOSFET occurs when VOUT = 0 (i.e. short

circuit). In this case the worst-case dissipation rises to:

SYNC

SC AVG

DS ON

= 







()

( )

With the 0.033

Ω sense resistor ISC(AVG) = 4A will result,

increasing the Si4412DY dissipation to 950mW at a die

temperature of 105

°C.

CIN is chosen for an RMS current rating of at least 1.5A at

temperature. COUT is chosen with an ESR of 0.03Ω for low

output ripple. The output ripple in continuous mode will be

highest at the maximum input voltage. The output voltage

ripple due to ESR is approximately:

ORIPPLE

ESR

()=

() =

∆Ω

003

1 3

P- P

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1436A/LTC1437A. These items are also illustrated

graphically in the layout diagram of Figure 15. Check the

following in your layout:

1. Are the signal and power grounds segregated? The

LTC1436A/LTC1437A signal ground pin must return to

the (–) plate of COUT. The power ground connects to the

source of the bottom N-channel MOSFET, anode of the

Schottky diode, and (–) plate of CIN, which should have

as short lead lengths as possible.

2. Does the LTC1436A/LTC1437A VOSENSE pin connect to

the (+) plate of COUT? In adjustable applications, the

resistive divider R1/R2 must be connected between the

(+) plate of COUT and signal ground. The 100pF capaci-

tor should be as close as possible to the LTC1436A/

LTC1437A.

3. Are the SENSE – and SENSE+ leads routed together with

minimum PC trace spacing? The filter capacitor be-

tween SENSE+ and SENSE– should be as close as

possible to the LTC1436A/LTC1437A.

4. Does the (+) plate of CIN connect to the drain of the

topside MOSFET(s) as closely as possible? This capaci-

tor provides the AC current to the MOSFET(s).

5. Is the INTVCC decoupling capacitor connected closely

between INTVCC and the power ground pin? This ca-

pacitor carries the MOSFET driver peak currents.

6. Keep the switching node SW away from sensitive small-

signal nodes. Ideally, the switch node should be placed

at the furthest point from the LTC1436A/LTC1437A.

7. Route the PLLIN line away from Boost and SW pins to

avoid unwanted pickup (Boost and SW pins have high

dV/dTs).

8. SGND should be used exclusively for grounding exter-

nal components on PLL LPF, COSC, ITH, LBI, SFB,

VOSENSE and AUXFB pins.

9. If operating close to the minimum on-time limit, is the

sense resistor oriented on the radial axis of the induc-

tor? See Figure 13.

LTC1436AIGN Datasheet(PDF) 23 Page - Linear Technology

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