UPD75P238 datasheet(21/50 Pages) NEC

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µPD75P238

VPP

VDD

5.3

PROGRAM MEMORY READ PROCEDURE

µPD75P238 program memory contents can be read using the following procedure. Reading is performed in

verify mode.

(1)

Unused pins are connected to VSS. The X1 pin is driven low.

(2)

5 V is supplied to the VDD and VPP pins.

(3)

µs wait.

(4)

Program memory address zero-clear mode.

(5)

6 V supplied to VDD, and 12.5 V to VPP.

(6)

Program inhibit mode.

(7)

Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per

4-pulse-input cycle.

(8)

Program inhibit mode.

(9)

Program memory address zero-clear mode.

(10) VDD / VPP pin voltage is changed to 5 V.

(11) Power-off.

Steps (2) to (9) of this procedure are shown in Fig. 5-2.

P40 to P43

P50 to P53

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

Fig. 5-2 Program Memory Read Timing

VDD

VDD +1

VDD

VPP

Data Output

"L"

UPD75P238 Datasheet(PDF) 21 Page - NEC

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