Electronic Components Datasheet Search
  English  ▼

X  

LTC1520CS Datasheet(PDF) 5 Page - Linear Technology

Part # LTC1520CS
Description  50Mbps Precision Quad Line Receiver
PDF  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1520CS Datasheet(HTML) 5 Page - Linear Technology

  LTC1520CS Datasheet HTML 1Page - Linear Technology LTC1520CS Datasheet HTML 2Page - Linear Technology LTC1520CS Datasheet HTML 3Page - Linear Technology LTC1520CS Datasheet HTML 4Page - Linear Technology LTC1520CS Datasheet HTML 5Page - Linear Technology LTC1520CS Datasheet HTML 6Page - Linear Technology LTC1520CS Datasheet HTML 7Page - Linear Technology LTC1520CS Datasheet HTML 8Page - Linear Technology  
Zoom Inzoom in Zoom Outzoom out
 5 / 8 page
background image
5
LTC1520
SWITCHI G TI E WAVEFOR S
APPLICATIONS INFORMATION
3.3V
≥18k
≥18k
A
B
RECEIVER ENABLED, VDD = 5V
RECEIVER DISABLED OR VDD = 0V
3.3V
≥18k
A
B
1520 F05
≥18k
Figure 5. Input Thevenin Equivalent
EQUIVALE T I PUT NETWORKS
Theory of Operation
Unlike typical line receivers whose propagation delay can
vary by as much as 500% from package to package and
show significant temperature drift, the LTC1520 employs
a novel architecture that produces a tightly controlled and
temperature compensated propagation delay. The differ-
ential timing skew is also minimized between rising and
VDD/2
VDD/2
VDD/2
VDD/2
3V
B1, B2 = 2.5V
2V
CH1 OUT
INPUT
A1, A2
CH2 OUT
tCH-CH
tCH-CH
1520 F03
Figure 3. Any Channel to Any Channel Skew, Same Package
Figure 4. Package-to-Package Propagation Delay Skew
falling output edges, and the propagation delays of any
two receivers within a package are very tightly matched.
The precision timing features of the LTC1520 reduce
overall system timing constraints by providing a narrow
6ns window during which valid data appears at the re-
ceiver output. This output timing window applies to all
receivers in all packages over all operating temperatures
Figure 2. Receiver Enable and Disable Timing
Test Circuit and Waveforms
1.5V
1.5V
1.5V
CL
1k
1k
S1
S2
tZH
tZL
1.5V
tLZ
0.2V
0.2V
tHZ
VDD
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH
0V
3V
ENABLE
5V
VOL
VOH
0V
RECEIVER
OUTPUT
OUT 1
OUT 1
1520 F02
SAME INPUT FOR BOTH PACKAGES
INPUT
A1, B1
VID = 500mV
PACKAGE 1
OUT 1
1520 F04
tPKG-PKG
tPKG-PKG
PACKAGE 2
OUT 1



Html Pages

1 2 3 4 5 6 7 8


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com