LTC1629CG datasheet(13/28 Pages) LINER

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LTC1629/LTC1629-PG

OUT

where k = 1, 2, …, N – 1

So the number of phases used can be selected to minimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In applica-

tions having a highly varying input voltage, additional

phases will produce the best results.

Accepting larger values of

∆IL allows the use of low

inductances, but can result in higher output voltage ripple.

A reasonable starting point for setting ripple current is

∆IL

= 0.4(IOUT)/N, where N is the number of channels and IOUT

is the total load current. Remember, the maximum

∆IL

occurs at the maximum input voltage. The individual

inductor ripple currents are constant determined by the

inductor, input and output voltages.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple.

not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive than

ferrite. A reasonable compromise from the same manu-

facturer is Kool M

µ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they lack a bobbin, mounting is more difficult.

However, designs for surface mount are available which

do not increase the height significantly.

Power MOSFET, D1 and D2 Selection

Two external power MOSFETs must be selected for each

controller with the LTC1629: One N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCC volt-

age. This voltage is typically 5V during start-up (see

EXTVCC Pin Connection). Consequently, logic-level thresh-

old MOSFETs must be used in most applications. The only

exception is if low input voltage is expected (VIN < 5V);

then, sublogic-level threshold MOSFETs (VGS(TH) < 3V)

should be used. Pay close attention to the BVDSS specifi-

cation for the MOSFETs as well; most of the logic-level

MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”

resistance RDS(ON), reverse transfer capacitance CRSS,

input voltage, and maximum output current. When the

LTC1629 is operating in continuous mode the duty factors

for the top and bottom MOSFETs of each output stage are

given by:

Main Switch Duty Cycle

OUT

Synchronous Switch Duty Cycle

OUT

= 







–

Kool M

µ is a registered trademark of Magnetics, Inc.

APPLICATIO S I FOR ATIO

Figure 3. Normalized Peak Output Current vs

Duty Factor [IRMS ≈ 0.3 (∆IO(P–P))]

DUTY FACTOR (VOUT/VIN)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1629 F03

6-PHASE

4-PHASE

3-PHASE

2-PHASE

1-PHASE

Inductor Core Selection

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite, molypermalloy, or Kool M

µ® cores. Actual core

loss is independent of core size for a fixed inductor value,

but it is very dependent on inductance selected. As induc-

tance increases, core losses go down. Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

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