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LTC1685 Datasheet(PDF) 11 Page - Linear Technology |
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LTC1685 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 12 page ![]() 11 LTC1685 APPLICATIONS INFORMATION single-ended trace over an adjacent ground plane. Then set the (bypassed) negative input of the receiver to roughly 2.5V. Note that single-ended operation might not reach maximum speeds. High Speed Differential SCSI (Fast-20, Fast-40 HVD) The LTC1685’s high speed, tight propagation delay win- dow and matched driver/receiver propagation delays make it a natural choice as the external transceiver in high speed differential SCSI applications. Note that the ±3.5ns propa- gation delay window covers the entire commercial tem- perature range. If, for example, a group of 16 transceivers is placed on the same board, their temperature difference will be much smaller. Hence, the difference in their propa- gation delays should be even better than the ±3.5ns specification (typically better than ±2ns). The LTC1685 is the most efficient and reliable implementation that meets the Fast-20 and Fast-40 HVD driver and receiver skew specifications. Power-Up Requirements The LTC1685 has unique short-circuit protection that shuts off the big output devices (and keeps them off) when a short is detected. When the LTC1685 is powered up with the driver outputs enabled (Figure 15 shows a typical connection), the part will power up in short-circuit mode. After power-up, the user must hold the DE pin of the LTC1685 low for at least 200ns in order to start normal operation. Note also that turning the termination power on/off might induce the LTC1685 to see a “short.” Conse- quently, the DE pin should be held low for 200ns after cable termination power is turned on. This requirement is solely due to the cable termination (the 165 Ω parallel resistance to both power and ground). For applications whose connections to the cable are made exclusively with RS485 devices, the cable can be terminated only across the two signal wires (as in Figure 10). With cable distances covering under 25 meters, the common mode range of the LTC1685 should be more than sufficient to account for any ground differences between any two communicating devices. The fact that transmission is differential should greatly improve noise TERM POWER 150 Ω 330 Ω 330 Ω 330 Ω 330 Ω A 1 4 EN RO 1685 F15 1/4 LTC1518 LTC1685 LTC1685 12 3 2 B 7 6 3 2 DE DI RO RE TERM POWER 122 Ω CABLE 4 1 150 Ω 7 6 3 2 DE DI RO RE 4 1 EN Figure 15. Fast-20, Fast-40 Differential SCSI Application Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. margin. Furthermore, the good high frequency CMRR of the receiver will serve to reject any common mode interference. DE, DI Inputs It is not necessary that the driver input (DI) have 0V to 3V signal levels. The DI input can be driven by CMOS levels (0V to 5V) and still achieve 40Mbps operation. However, duty cycle will be slightly compromised when driven by a CMOS device. Care should be taken to minimize the ringing on the DI input in order to achieve a driver propagation delay within the ±3.5ns window. This also improves the package-to-package matching of propaga- tion delays. The DE pin should be held low for 200ns after the power- up sequence has been completed. After fault conditions such as an output short or thermal shutdown, the DE pin should be held low for at least 200ns after the fault has been removed. This is usually necessary only if the driver outputs are connected to DC-biased cable terminations (as in Figure 15). Layout Considerations A ground plane is recommended when using a high frequency device like the LTC1685. A 0.1 µF ceramic by- pass capacitor less than 1/4 inch away from the VDD pin is recommended. Good bypassing is especially needed when operating at maximum frequency or when package-to- package matching is very important. The PC board traces connected to the “A” and “B” outputs must be kept as symmetrical and short as possible to obtain the same |
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