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LTC1703

capacitors and/or paralleling multiple capacitors at the

output. The capacitance value accounts for the rest of the

voltage drop until the inductor current rises. With most

output capacitors, several devices paralleled to get the

ESR down will have so much capacitance that this drop

term is negligible. Ceramic capacitors are an exception; a

small ceramic capacitor can have suitably low ESR with

relatively small values of capacitance, making this second

drop term significant.

Optimizing Loop Compensation

Loop compensation has a fundamental impact on tran-

sient recovery time, the time it takes the LTC1703 to

recover after the output voltage has dropped due to output

capacitor ESR. Optimizing loop compensation entails

maintaining the highest possible loop bandwidth while

ensuring loop stability. The Feedback Component Selec-

tion section describes in detail how to design an optimized

feedback loop, appropriate for most LTC1703 systems.

Voltage Positioning

If the load transients consist primarily of load steps from

near zero load to full load and back, the transient response

can be traded off against DC regulation performance by

using a technique known as “voltage positioning.” The

goal is to intentionally compromise the DC regulation loop

such that the output rides near the maximum allowable

value (often +5%) with no load and near the minimum

allowable value at maximum load. With the load at zero,

any transient that comes along will be a current increase

which will cause the output voltage to fall. Since the output

voltage is initially at a high value, it can fall further before

it goes out of spec. Similarly, at full load, the output current

can only decrease, causing a positive shift in the output

voltage; the initial low value allows it to rise further before

the spec is exceeded. The primary benefit of voltage

positioning is it increases the allowable ESR of the output

capacitors, saving cost. An additional bonus is that at

maximum load, the output voltage is near the minimum

allowable, decreasing the power dissipated in the load.

Implementing voltage positioning is as simple as creating

an intentional resistance in the output path to generate the

required voltage drop. This resistance can be a low value

resistor, a length of PCB trace, or even the parasitic

resistance of the inductor if an appropriate filter is used. If

the LTC1703 senses the output voltage upstream from the

resistance (Figure 17c), the output voltage will move with

load as I • RVP, where I is the load current and RVP is the

value of the voltage positioning resistor. If the feedback

network is then reset to regulate near the upper edge of the

LTC1703

1703 F17a

1703 F17b

VOUT

VIN

+5%

–5%

NOM

MAX

VOUT

LOAD

CURRENT

MAXIMUM

ALLOWABLE

TRANSIENT

Figure 17a. Standard Regulator

Figure 17b. Standard Regulator—Transient Response

LTC1703

1703 F17c

1703 F17d

VOUT

VIN

RVP

+5%

–5%

NOM

MAX

VOUT

LOAD

CURRENT

Figure 17c. Voltage Positioning Regulator

Figure 17d. Positioning Regulator—Transient Response

MAXIMUM

ALLOWABLE

TRANSIENT

≈2× FIGURE 17b

APPLICATIO S I FOR ATIO

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