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LTC1710CS8 Datasheet(PDF) 3 Page - Linear Technology |
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LTC1710CS8 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 8 page ![]() 3 LTC1710 ELECTRICAL CHARACTERISTICS T A = 25°C, VCC = SW0D = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tON Output Turn-On Time VCC = 2.7V (From ON (Note 6) to VOUT = 90% VCC) 200 µs (100 Ω/1µF Load) VCC = 5.5V (From ON (Note 6) to VOUT = 90% VCC) 160 µs tOFF Output Turn-Off Time VCC = 2.7V (From OFF (Note 7) to VOUT = 10% VCC) 250 µs (100 Ω/1µF Load) VCC = 5.5V (From OFF (Note 7) to VOUT = 10% VCC) 250 µs VIL DATA/CLK Input Low Voltage VCC = 2.7V to 5.5V q 0.6 V AD1 Input Low Voltage VCC = 2.7V to 5.5V q 0.2 V VIH DATA/CLK High Voltage VCC = 2.7V to 5.5V q 1.4 V AD1 Input High Voltage VCC = 2.7V to 5.5V q VCC – 0.2 V VOL Data Output Low Voltage VCC = 2.7V to 5.5V, IPULL-UP = 350µA q 0.18 0.4 V CIN Input Capacitance (DATA, CLK, AD1) 5 pF IIN Input Leakage Current (DATA, CLK) q ±1 µA Input Leakage Current (AD1) q ±250 nA SMBus Related Specifications (Note 5) fSMB SMBus Operating Frequency 10 100 kHz tBUF Bus Free Time Between 4.7 µs Stop and Start tSU:STA Start Condition Setup Time 4.7 µs tHD:STA Start Condition Hold Time 4.0 µs tSU:STO Stop Condition Setup Time 4.0 µs tHD: DAT Data Hold Time 300 ns tSU:DAT Data Setup Time 250 ns tLOW Clock Low Period 4.7 µs tHIGH Clock High Period 4.0 50 µs tf Clock/Data Fall Time 300 ns tr Clock/Data Rise Time 1000 ns IPULL-UP Current Through External Pull-Up VCC = 2.7V to 5.5V 100 350 µA Resistor on DATA Pin (Open-Drain Data Pull-Down Current Capacity) The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Approximately 3% hysteresis is provided to ensure stable operation and eliminate false triggering by minor VCC glitches. Note 3: Measured from VCC > VUVLO to SMBus ready for DATA input. Note 4: The oscillator frequency is not tested directly but is inferred from turn-on time. Note 5: SMBus timing specifications are guaranteed but not tested. Note 6: ON is enabled upon receiving the Stop condition from the SMBus master. Note 7: OFF is enabled upon receiving the Stop condition from the SMBus master. |
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