LTC2400CS8 datasheet(20/40 Pages) LINER

20 / 40 page

LTC2400

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data output

cycle begins on the first rising edge of SCK and ends after

the 32nd rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used

to shift the conversion result into external circuitry. EOC

can be latched on the first rising edge of SCK and the last

bit of the conversion result can be latched on the 32nd

rising edge of SCK. After the 32nd rising edge, SDO goes

HIGH (EOC = 1) indicating a new conversion is in progress.

SCK remains HIGH during the conversion.

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 11. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 12 and 13. Once the

voltage at CS falls below an internal threshold (

≈1.4V), the

device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 32nd rising edge. Data is shifted out the SDO

APPLICATIONS INFORMATION

SDO

Hi-Z

SCK

(INTERNAL)

VCC

GND

2400 F11

VCC

VREF

SCK

VIN

SDO

GND

CEXT

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

µF

2.7V TO 5.5V

LTC2400

BIT 0

SIG

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

EOC

BIT 31

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

Figure 11. Internal Serial Clock, Autostart Operation

LTC2400CS8 Datasheet(PDF) 20 Page - Linear Technology

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