LTC2428C datasheet(6/28 Pages) LINER

6 / 28 page

LTC2424/LTC2428

PIN FUNCTIONS

GND (Pins 1, 6, 16, 18, 22, 27, 28): Ground. Should be

connected directly to a ground plane through a minimum

length trace or it should be the single-point-ground in a

single-point grounding system.

VCC (Pins 2, 8): Positive Supply Voltage. 2.7V ≤ VCC ≤

5.5V. Bypass to GND with a 10

µF tantalum capacitor in

parallel with 0.1

µF ceramic capacitor as close to the part

as possible.

FSSET (Pin 3): Full-Scale Set Input. This pin defines the

full-scale input value. When VIN = FSSET, the ADC outputs

full scale (FFFFFH). The total reference voltage (VREF) is

FSSET – ZSSET.

ADCIN (Pin 4): Analog Input. The input voltage range is

– 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input

voltage range may be limited by the pin absolute maxi-

mum rating of – 0.3V to VCC + 0.3V.

ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the

zero-scale input value. When VIN = ZSSET, the ADC outputs

zero scale (00000H).ForpincompatibilitywiththeLTC2404/

LTC2408 this pin must be grounded.

MUXOUT (Pin 7): MUX Output. This pin is the output of the

multiplexer. Tie to ADCIN for normal operation.

CH0 (Pin 9): Analog Multiplexer Input.

CH1 (Pin 10): Analog Multiplexer Input.

CH2 (Pin 11): Analog Multiplexer Input.

CH3 (Pin 12): Analog Multiplexer Input.

CH4 (Pin 13): Analog Multiplexer Input. No connect on the

LTC2424.

CH5 (Pin 14): Analog Multiplexer Input. No connect on the

LTC2424.

CH6 (Pin 15): Analog Multiplexer Input. No connect on the

LTC2424.

CH7 (Pin 17): Analog Multiplexer Input. No connect on the

LTC2424.

CLK (Pin 19): Shift Clock for Data In. This clock synchro-

nizes the serial data transfer into the MUX. For normal

operation, drive this pin in parallel with SCK.

CSMUX (Pin 20): MUX Chip Select Input. A logic high on

this input allows the MUX to receive a channel address. A

logic low enables the selected MUX channel and connects

it to the MUXOUT pin for A/D conversion. For normal

operation, drive this pin in parallel with CSADC.

DIN (Pin 21): Digital Data Input. The multiplexer address

is shifted into this input on the last four rising CLK edges

before CSMUX goes low.

CSADC (Pin 23): ADC Chip Select Input. A low on this pin

enables the SDO digital output and following each conver-

sion, the ADC automatically enters the Sleep mode and

remains in this low power state as long as CSADC is high.

A high on this pin also disables the SDO digital output. A

low-to-high transition on CSADC during the Data Output

state aborts the data transfer and starts a new conversion.

For normal operation, drive this pin in parallel with CSMUX.

SDO (Pin 24): Three-State Digital Output. During the data

output period this pin is used for serial data output. When

the chip select CSADC is high (CSADC = VCC), the SDO pin

is in a high impedance state. During the Conversion and

Sleep periods, this pin can be used as a conversion status

output. The conversion status can be observed by pulling

CSADC low.

SCK (Pin 25): Shift Clock for Data Out. This clock synchro-

nizes the serial data transfer of the ADC data output. Data

is shifted out of SDO on the falling edge of SCK. For normal

operation, drive this pin in parallel with CLK.

FO (Pin 26): Digital input which controls the ADC’s notch

frequencies and conversion time. When the FO pin is

connected to VCC (FO = VCC), the converter uses its internal

oscillator and the digital filter first null is located at 50Hz.

When the FO pin is connected to GND (FO = OV), the

converter uses its internal oscillator and the digital filter

first null is located at 60Hz. When FO is driven by an

external clock signal with a frequency fEOSC, the converter

uses this signal as its clock and the digital filter first null is

located at a frequency fEOSC/2560. The resulting output

word rate is fEOSC/20480.

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