LF3304 datasheet(2/12 Pages) LODEV

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DEVICES INCORPORATED

LF3304

Dual Line Buffer/FIFO

Video Imaging Products

08/16/2000–LDS.3304-F

the data presented on LENGTH11-0 is

loadedintothedeviceontheactiveedgeof

WCLKAinconjunctionwithLDAbeing

drivenLOW. TosetthelengthofRAM

Array B the data presented on

LENGTH11-0 is loaded into the device

on the active edge of WCLKB in

conjunction with LDB being driven

LOW. If an equal length is desired for

both RAM Arrays, the data presented

on LENGTH11-0 is loaded into the

device on the active edge of WCLK

(WCLKA and WCLKB tied together) in

conjuction with LDx (LDA and LDB

tied together) being driven LOW.

MODE1-0 — Mode Select

Themodeselectinputsdeterminethe

operatingmodeoftheLF3304(Table1)for

data being input on the next clock cycle.

Whenswitchingbetweenmodes,the

internal pipeline latencies of the device

mustbeobserved. Afterswitching

operatingmodes,eithertheusermust

allow enough clock clycles to pass to flush

the internal RAM Array or RWx and RRx

mustbedrivenLOWtogetherbeforevalid

data will appear on the outputs.

Controls

LDA — RAM Array A Load

When LDA is LOW, data on

LENGTH11-0 is latched in the length

LDB — RAM Array B Load

When LDB is LOW, data on

LENGTH11-0 is latched in the length

WENA — Write Enable A

DrivingWENALOWplacesthedevicein

programmabledelaymodeanddriving

WENA HIGH places RAM Array A in

recirculatemode(programmablecircular

buffer). Wheninrecirculatemode,the

write pointer position remains fixed while

data on AIN11-0 is ignored. When

switchingbackfromrecirculatemodeto

MODE1-0

Mode Select

Dual Line Buffer

Cascaded Line Buffer

Dual FIFO

Reserved

delay mode, RWA and RRA should be

broughtLOWtoproperlyresettheWrite

and Read pointers.

RENA — Read Enable B

In Line Buffer mode, RENA must be

kept LOW.

WENB — Write Enable B

Driving WENB LOW places the device in

programmabledelaymodeanddriving

WENB HIGH places RAM Array B in

recirculatemode(programmablecircular

buffer). Wheninrecirculatemode,the

write pointer position remains fixed

while data on BIN11-0 is ignored. When

switching back from recirculate mode to

delay mode, RWB and RRB should be

brought LOW to properly reset the Write

and Read pointers.

RENB — Read Enable B

In Line Buffer mode, RENB must be

kept LOW.

RWA — Reset Write A

The write address pointer is reset to the

first physical location when RWA is set

LOW. After power up, the LF3304

requires a Reset Write for initialization

because the write address pointer is not

defined at that time.

RRA — Reset Read A

The read address pointer is reset to the

first physical location when RRA is set

LOW. After power up, the LF3304

requires a Reset Read for initialization

because the read address pointer is not

defined at that time.

LINE BUFFER MODE

SIGNAL DEFINITIONS

Power

VCC and GND

+3.3 V power supply. All pins must

be connected.

Clocks

WCLKA — Write Clock A

WCLKA and RCLKA must be tied

togetherforRAMArrayAtoproperly

operate as a Line Buffer. The rising edge

of xCLKA strobes all appropriate

enabledregisters.

RCLKA — Read Clock A

See WCLKA description.

WCLKB — Write Clock B

WCLKB and RCLKB must be tied

together for RAM Array B to properly

operate as a Line Buffer. The rising

edge of xCLKB strobes all appropriate

enabledregisters.

RCLKB — Read Clock B

See WCLKB description.

Inputs

AIN11-0 — Data Input A

AIN11-0 is the 12-bit registered data

input port.

BIN11-0 — Data Input B

BIN11-0 is the 12-bit registered data

input port.

LENGTH11-0 — Line Buffer Length

The 12-bit value is used to specify the

length of each of the RAM Arrays. An

integer value ranging from 0 to 4095 is

used to select a delay ranging from 2 to

4097 clock cycles. The value placed on

LENGTH11-0 is equal to the desired delay

minus8. TosetthelengthofRAMArrayA

TABLE 1.

DEVICE CONFIGURATION

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