8

1.2 Bus Interface Pins

The

µPD98409 employs a 32-bit PCI bus interface as a bus interface with the host. This interface conforms to

“PCI Local Bus Specification Revision 2.1”.

(1/2)

Pin Name

Pin No.

I/O

I/O Level

Function

AD31-AD0

238, 239,

3 - 6,

9, 10,

16 - 19,

22 - 25,

42 - 45,

48 - 51,

55 - 57,

62 - 65,

68

I/O

3-state

PCI

Address/data.

AD31 through AD0 are 32 bits of multiplexed address and data bus

signals. When the

µPD98409 operates as the bus master, it drives an

address at the first one clock, and transfers data at the second clock

and onward.

PCBE3_B

PCBE2_B

PCBE1_B

PCBE0_B

11,

27,

39,

54

I/O

3-state

PCI

Bus command and byte enable.

These signals define “bus commands” (generated bus transaction) in an

address phase. In a data phase, they indicate which byte lane holds

valid data. The PCBE3_B pin corresponds to byte 3 (bits 31 through

24), and PCBE0_B pin corresponds to byte 0 (bits 7 through 0).

PAR

38

I/O

3-state

PCI

Parity.

This signal inputs/outputs an even parity on the AD31 through AD0

and PCBE3_B through PCBE0_B pins including the PAR signal.

When the

µPD98409 operates as the master, the PAR signal is output

in the address and write data phases. When the

µPD98409 operates

as a target, the PAR signal is output in the read data phase.

FRAME_B

28

I/O

Sustained

3-state

PCI

Frame.

This signal indicates the start and period of bus transaction. When

this signal becomes active, it indicates the start of bus transaction.

While it is active, data is transferred. When the next data transfer

phase is for the last data of the transaction, this signal becomes

inactive.

TRDY_B

30

I/O

Sustained

3-state

PCI

Target ready.

This signal goes low when the target device is ready to complete the

transaction of the current data phase. This signal is used in pairs with

IRDY_B. When both IRDY_B and TRDY_B are low, read/write data

transfer is executed.

IRDY_B

29

I/O

Sustained

3-state

PCI

Initiator ready.

This signal goes low when the initiator is ready to complete the

transaction of the current data phase. This signal is used in pairs with

TRDY_B. When both IRDY_B and TRDY_B are low, read/write data

transfer is executed. If both FRAME_B and IRDY_B are inactive, the

bus cycle is not executed, and wait cycles are inserted until both

IRDY_B and TRDY_B become active.