RDD104 datasheet(2/2 Pages) LSI

2 / 2 page

DYNAMIC ELECTRICAL CHARACTERISTICS:

(CL = 50pF, Input Rise and Fall Times = 20ns except for Clock,

unless otherwise specified.)

VDD

MIN

MAX

UNIT

Clock Input Frequency

4.5V

1.5

MHz

10V

4.0

MHz

15V

6.0

MHz

Clock Input Rise & Fall Times

4.5 to 15V

No Limit

Clock Input Rise & Fall Time,

4.5V

140

CL = 15pF

10V

Clock Output Propagation

4.5V

300

Delay, CL = 15pF

10V

150

Output Rise & Fall Times

4.5V

400

10V

200

Propagation Delay to Output

4.5V

1500

10V

750

Reset Pulse Width

4.5V

800

10V

400

Reset Removal Time

4.5V

500

10V

250

Reset Propagation Delay

4.5V

1400

to Output

10V

700

Select Input Setup Time

4.5V

800

10V

400

MINIMUM PARTS OSCILLATOR CIRCUIT

PIN 6

10M

PIN 5

FIGURE 2.

TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW

PIN 5

PIN 6

20M

10M

100pF

40pF

FIGURE 3.

PIN 5

PIN 6

39pF

10M

FIGURE 4.

TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ

56pF

50pF

20pF

CLOCK

INPUT

SIGNAL

V SS

V DD

FIGURE 5. TYPICAL INPUT

If input signals are less than VSS or greater than

VDD, a series input resistor, R1, should be used to

limit the maximum input current to 2 milliamperes.

BUFFER

-V

1 OUT OF 4 SELECTOR

DECODER

FIGURE 6.

RDD 104 BLOCK DIAGRAM

CLOCK

GENERATOR

CLOCK IN

CLOCK OUT

RESET

DIVIDER SELECT-1

DIVIDER SELECT-2

OSCILLATOR

EXTERNAL

COMPONENTS

OUTPUT

V DD

V SS

3 STAGE INVERTING

AMPLIFIER

RDD104-011000-2

RDD104 Datasheet(PDF) 2 Page - LSI Computer Systems

RDD104 Datasheet(HTML) 2 Page - LSI Computer Systems

Html Pages

1 2

Datasheet Download

Link URL