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LT3582/LT3582-5/LT3582-12

3582512fb

APPLICATIONS INFORMATION

Note that the ripple voltage on VOUTP will typically increase

in this conﬁguration since the output disconnect PMOS,

when not shorted, helps to create an RC ﬁlter at the

output. Also, if the VOUTP pin is shorted to CAPP, the

power-down discharge should not be enabled. VOUTP

cannot be discharged to ground during shutdown due to

the path from VIN to VOUTP through the external inductor

and diode. Finally, due to the path from VIN to VOUTP,

current will ﬂow through the integrated feedback resistor

whenever voltage is present on VIN.

Inrush Current

When the Boost inductor input voltage (usually VIN) is

stepped from ground to the operating voltage, a high

level of inrush current may ﬂow through the inductor

and Schottky diode into the CAPP capacitor. Conditions

that increase inrush current include a larger more abrupt

voltage step at the inductor input, larger CAPP capacitors

and inductors with low inductances and/or low saturation

currents. For circuits that use output capacitor values within

the recommended range and have input voltages of less

than 5V, inrush current remains low, posing no hazard to

the devices. In cases where there are large input voltage

steps (more than 5V) and/or a large CAPP capacitor is

used, inrush current should be measured to ensure safe

operation.

Thermal Lockout

If the die temperature reaches approximately 147°C, the

part will go into thermal lockout. In this event, the chip

is reset which turns off the power switches and starts to

discharge the RAMP capacitors. The part will be re-enabled

when the die temperature drops by about 3.5°C.

Board Layout Considerations

As with all switching regulators, careful attention must be

paid to the PCB board layout and component placement. To

maximize efﬁciency, switch rise and fall times are made as

short as possible. To prevent electromagnetic interference

(EMI) problems, proper layout of the high frequency

switching path is essential. The voltage signals of the

SWP and SWN pins have sharp rising and falling edges.

Minimize the length and area of all traces connected to

the SWP/SWN pins and always use a ground plane under

the switching regulator to minimize interplane coupling.

Suggested component placement is shown in Figure 12.

Make sure to include the ground plane cuts as shown in

Figure 12. The switching action of the regulators can cause

large current steps in the ground plane. The cuts reduce

noise by recombining the current steps into a continuous

ﬂow under the chip, thus reducing di/dt related ground

noise in the ground plane.

Figure 12. Suggested Component Placement (Not to Scale)

GROUND PLANE

VIAS TO GROUND PLANE UNDER

PIN 17 REQUIRED TO IMPROVE

THERMAL PERFORMANCE

3582512 F13

VOUTP

COUTP

CCAPP

COUTN

VOUTN

GND

VIN

CIN

CVPP

(OPT)

SCL

SDA

VPP

SHDN

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