16 of 36

RF2053

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Start-up

When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500ecs.

before ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. After taking ENBL high there

is typically 20usecs for the PLL state machine and charge pump to initialize, the VCO warm-up state, before PLL locking starts.

The time spent in the VCO warm-up state is set by CFG1:TVCO, which should be set to 00111 when using a 26MHz clock. Fol-

lowing the warm-up period there will be the additional time taken for the PLL to settle to the required frequency. All of these

timings will be dependent upon application specific factors such as loop filter bandwidth, reference clock frequency, and XO

characteristics. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration

routines (always the case for the RF2053), minimizing the VCO warm-up time, and setting the PLL loop bandwidth as wide as

possible.

The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting

the RESETB pin low for at least 100ns.

Setting Up Device Operation

The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is

achieved as follows.

Three registers need to be written, taking 3.9us at the maximum clock speed.

Se t-u p de vice

operatio n

Active loop

filte r?

De fa u lt

No

PD P se t to 0

Progra m

MIX 2 _ID D

S e t-u p co m p le te

Progra m X O _C T ,

XO _C R _S and

CL K _D IV

In te rn a l

ca p a cito rs

u s e d to se t

Xta l lo ad

Mixe r

lin e a rity

1

2

To se t u p R F 2 0 5 3 o p e ra tio n w ith a n e xte rn a l V C O it is

n e ce ssa ry to se t th e E X T _ V C O b it in C FG 1 re g iste r h ig h

an d to a lw a ys se le ct V C O 3 to ro u te th e V C O in p u t

th ro u g h to th e syn th e size r. T h e L F_ A C T b it in C F G 1

re giste r sho u ld b e se t to 0 a s a n e xte rn a l o p -a m p is

n o rm a lly u sed in th e loop filter.

Th e m ixe r lin e a rity se ttin g is th e n se le cte d . T h e d e fa u lt

va lu e is 4 w ith 1 b e in g th e lo w e st se ttin g a n d 5 th e

h ig h e st. Th e M IX 2 _ ID D b its a re lo ca te d in th e C F G 2

re giste r.

Th e in te rn al crysta l lo adin g ca p a cito rs are also

p ro gra m m e d to p re se n t th e co rre ct lo a d to th e crysta l.

Th e ca p a cita n ce in te rn a l to th e ch ip ca n b e varie d

from 8 -1 6 p F in 0.2 5 p F ste p s (d e fa u lt=1 0p F). T h e

re fe re n ce d ivid e r m u st a lso b e se t to d e te rm in e th e

ph a se d e te cto r fre q u e n cy (d efa u lt=1 ). Th ese b its a re

lo ca te d in th e C F G 4 re g iste r.

Progra m

EX T_VC O = 1

P2 _V CO SEL= 10

LF _A C T = 0

W h e n se ttin g u p th e d e vice it is n e ce ssa ry to d e cid e if

an a ctive or p assive loop filter w ill b e u sed in th e

ph a se lo ck ed lo op. Set th e p h a se dete ctor p o la rity b it

in C FG 1 sin ce th e a ctive filter in ve rts th e loop filter

vo lta ge. N o rm a lly a ctive lo o p filte r w ith a n e xte rn a l o p -

am p is u sed w ith th e RF 205 3 , so se t PD P = 1, th e

defa u lt se ttin g.