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RFSA2724

DS130212

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at ((+1) 336-678-5570 or c

customerservice@rfmd.com.

Truth Table

Serial Port Interface

Control Bit

Relative Gain

Setting

C16

C8

C4

C2

C1

C0.5

C0.25

11

11

111

Max gain

11

11

110

-0.25dB

11

11

101

-0.5dB

11

11

011

-1dB

11

10

111

-2dB

11

01

111

-4dB

10

11

111

-8dB

01

11

111

-16dB

00

00

000

-31.75dB

Note: C0.25 = D0, C0.5 = D1, …, C16 = D6 (for the purpose of the example below)

SPI Timing Diagram Specifications

Parameter

Limit

Unit

Comment

Logic Voltage Levels

t1

25

MHz max

CLK Frequency

S

State

Logic

t2

20

ns min

CLK High

Low

0V to 0.8V

t3

20

ns min

CLK Low

High

2.0V to 5.0V

t4

5

ns min

DATA to CLK Setup Time

t5

5

ns min

DATA to CLK Hold Time

t6

30

ns min

DATA Valid

t7

5

ns min

LE to CLK Setup Time

t8

5

ns min

CLK to LE Setup Time

t9

10

ns min

LE Pulse Width

t10

20

ns max

Output Set

CLK

DATA

t6

LE

t1

t2

t3

t4

t5

t7

t8

DOUT

t9

SPI Timing Diagram

t10

Programming example – 7 bit

MSB

D5

D4

D3

D1

D2

D6

CLK

DATA

LE

LSB

D0