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CS5124 Datasheet(PDF) 7 Page - ON Semiconductor |
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CS5124 Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 11 page ![]() CS5124 http://onsemi.com 7 the Soft−Start error amp is clamped at 2.9 V. During fault conditions the Soft−Start capacitor is discharged at 10 mA. Fault Conditions The CS5124 recognizes the following faults: UVLO off, Thermal Shutdown, VREF(OK), and Second Current Threshold. Once a fault is recognized, fault latch F2 is set and the IC immediately shuts down the output driver and discharges the Soft−Start capacitor. Soft−Start will begin only after all faults have been removed and the Soft−Start capacitor has been discharged to less than 0.275 V. Each fault will be explained in the following sections. Under Voltage Lockout (UVLO) The UVLO pin is tied to typically the midpoint of a resistive divider between VIN and GROUND. During a start up sequence, this pin must be above 2.6 V in order for the IC to begin normal operation. If the IC is running and this pin is pulled below 1.8 V, F2 shuts down the output driver and discharges the Soft−Start capacitor in order to insure proper startup. If the UVLO pin is pulled high again before the Soft−Start capacitor discharges, the IC will complete the Soft−Start discharge and, if no other faults are present, will immediately restart the power supply. If the UVLO pin stays low, then it will enter either the low current sleep mode or the UVLO state depending on the level of the UVLO pin. Thermal Shutdown If the IC junction temperature exceeds approximately 150 °C the thermal shutdown circuit sets F2, which shuts down the output driver and discharges the Soft−Start capacitor. If no other faults are present the IC will initiate Soft−Start when the IC junction temperature has been reduced by 25 °C. VREF(OK) VREF(OK) is an internal monitor that insures the internal regulator is running before any switching occurs. This function does not trip the fault comparator like the other fault functions. To insure that Soft−Start will occur at low line conditions the UVLO divider should be set up so that the VCC UVLO comparator turns on before the LINE UVLO comparator. Second Threshold Comparator Since the maximum dynamic range of the ISENSE signal in normal operation is 195 mV, any voltage exceeding this threshold on the ISENSE pin is considered a fault and the PWM cycle is terminated. The 2nd ICOMP compares the ISENSE signal with a 275 mV threshold. If the ISENSE voltage exceeds the second threshold, F2 is set, the driver turns off, and the Soft−Start capacitor discharges. After the Soft−Start capacitor has discharged to less than 0.275 V Soft−Start will begin. If the fault condition has been removed the supply will operate normally. If the fault remains the supply will operate in hiccup mode until the fault condition is removed. VFB Comparator The VFB comparator detects when the output voltage is too high. When the regulated output voltage is too high, the feedback loop will drive VFB low. If VFB is less than 0.49 V the output of the VFB comparator will go high and shut the output driver off. Oscillator The internally trimmed, 400 kHz provides the slope compensation ramp as well as the pulse for enabling the output driver. PWM Comparator and Slope Compensation The CS5124 provides a fixed internal slope compensation ramp that is subtracted from the feedback signal. The PWM comparator compares peak primary current to a portion of the difference of the feedback voltage and slope compensation ramp. The 170 mV/ ms slope compensation ramp is subtracted from the voltage feedback signal internally. The difference signal is then divided by ten before the PWM comparator to provide high noise rejection with a low voltage across the current sense network. The effective ramp is 21 mV/ ms. A 60 mV nominal offset on the positive input to the PWM comparator allows for operation with the ISENSE pin at, or even slightly below GND. A 4.3 k W pull−up resistor internally connected to a 5.0 V nominal reference provides the bias current to for an optocoupler connection to the VFB pin. |
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