M30802SGP datasheet(28/315 Pages) MITSUBISHI

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Preliminary Specifications REV.B

Specifications in this manual are tentative and subject to change.

Mitsubishi microcomputers

M16C/80 (144-pin version) group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Settings

The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the

processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address

000516) are used to change the bus settings.

Table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width

control register and table 1.7.2 shows external area 0 to 3 and external area mode.

Bus setting

Switching factor

Switching external address bus width

External data bus width control register

Switching external data bus width

BYTE pin (external area 3 only)

Switching between separate and multiplex bus

Bits 4 and 5 of processor mode register 0

(1) Selecting external address bus width

You can select the width of the address bus output externally from the 16 Mbytes address space, the

number of chip select signals, and the address area of the chip select signals. (Note, however, that when

____

you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits 0 and

1 of the processor mode register 1 allow you to set the external area mode.

When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and

column addresses.

(2) Selecting external data bus width

You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When

the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;

when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for

external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after

a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits).

During operation, fix the level of the BYTE pin to “H” or “L”.

(3) Selecting separate/multiplex bus

The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.

• Separate bus

In this bus configuration, input and output is performed on separate data and address buses. The data

bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all

programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is

a programmable IO port. When the external data bus width is set to 16 bits for any of the external

areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus.

When accessing memory using the separate bus configuration, you can select a software wait using

the wait control register.

• Multiplex bus

In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas

for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7

are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the

external data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to

A15. When accessing memory using the multiplex bus configuration, two waits are inserted regard-

less of whether you select “No wait” or “1 wait’ in the appropriate bit of the wait control register.

Table 1.7.1. Factors for switching bus settings

M30802SGP Datasheet(PDF) 28 Page - Mitsubishi Electric Semiconductor

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