PDO is a rectangular current-pulse train, alternating

between 0µA and 500µA. It has a 50% duty cycle when

the MAX038 output and PDI are in phase-quadrature

(90° out of phase). The duty cycle approaches 100%

as the phase difference approaches 180° and con-

versely, approaches 0% as the phase difference

can be expressed as:

[16]

When the loop is in lock, the input signals to the phase

detector are in approximate phase quadrature, the duty

cycle is 50%, and the average current at PDO is 250µA

(the current sink of FADJ). This current is divided

phase difference increases, PDO duty cycle increases,

decreases the oscillator frequency, reducing the phase

difference, thus maintaining phase lock. The higher

ence; in other words, the greater the loop gain, the less

the capture range. The current from PDO must also

The phase error (deviation from phase quadrature)

depends on the open-loop gain of the PLL and the ini-

tial frequency deviation of the oscillator from the exter-

[17]

which, from equation [6] is:

[18]

[19]

where:

With a loop filter having a response F(s), the open-loop

transfer function, T(s), is:

[20]

Using linear feedback analysis techniques, the closed-

loop transfer characteristic, H(s), can be related to the

open-loop transfer function as follows:

H(s) = T(s) ÷ [1+ T(s)]

[21]

The transient performance and the frequency response

of the PLL depends on the choice of the filter charac-

teristic, F(s).

When the MAX038 internal phase detector is not used,

PDI and PDO should be connected to GND.

External Phase Detectors

External phase detectors may be used instead of the

internal phase detector. The external phase detector

shown in Figure 4 duplicates the action of the MAX038’s

internal phase detector, but the optional ÷N circuit can

be placed between the SYNC output and the phase

detector in applications requiring synchronizing to an

exact multiple of the external oscillator. The resistor net-

work consisting of R4, R5, and R6 sets the sync range,

while capacitor C4 sets the capture range. Note that

this type of phase detector (with or without the ÷N cir-

cuit) locks onto harmonics of the external oscillator as

well as the fundamental. With no external oscillator

input, this circuit can be unpredictable, depending on

the state of the external input DC level.

Figure 4 shows a frequency phase detector that locks

onto only the fundamental of the external oscillator.

With no external oscillator input, the output of the fre-

quency phase detector is a positive DC voltage, and

the oscillations are at the lowest frequency as set by

R4, R5, and R6.

High-Frequency Waveform Generator

______________________________________________________________________________________

13

MAX038

GND

COSC

12

A0

V-

18

11

9

2

6

GND GND

15

DGND

GND GND

5

8

10

7

1

13

3

FADJ

IIN

DADJ

REF

OUT

PDI

PDO

V+

A1

4

17

DV+

16

20

+5V -5V

C2

1µF

C1

1µF

CENTER

FREQUENCY

50

Ω

19

RF

OUTPUT

SYNC

14

EXTERNAL OSC INPUT

Figure 3. Phase-Locked Loop Using Internal Phase Detector